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Design >> High-Speed I/O Design >> CDR bool
https://designers-guide.org/forum/YaBB.pl?num=1246023562

Message started by splurk on Jun 26^th, 2009, 6:39am

Title: CDR bool
Post by splurk on Jun 26^th, 2009, 6:39am

Hello,

I have to design a CDR for a USB2 PHY (480Mbits/s) in CMOS technology (0.35um).
I'm looking for books that may help me to design the CDR as I don't really know where to start.
I tried some design extracted from some papers found on the net, but nothing really interesting, as they work more or less for ideal condition, but with jitter/temperature variation it starts to randomly work.
What miss me the most is probably some mathematics on precise examples.

Thanks a lot!

Title: Re: CDR bool
Post by casual on Dec 15^th, 2009, 6:44pm

There are many types of CDR topology eg PLL-based, DLL-based etc...
For USB and wired links, normally oversampling based CDRs are used. Check on "A 0.5-um CMOS 4.0-Gbitps Serial Link Transceiver with Data Recovery" Using Oversampling (CK Ken Yang, R. Farjad-Rad, M Horowitz). A typical journal for oversampling.

It is widely used due to all digital design. In other word, it can be designed with VHDL/Verilog as compared to the need of custom design in PLL.