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Modeling >> Semiconductor Devices >> PMOS and NMOS temperature coefficient
https://designers-guide.org/forum/YaBB.pl?num=1247771443

Message started by cmos.analogvala on Jul 16^th, 2009, 12:10pm

Title: PMOS and NMOS temperature coefficient
Post by cmos.analogvala on Jul 16^th, 2009, 12:10pm

I found in more than one technology that PMOS has positive temperature coefficient(IDS increases with temperature) whereas NMOS has negative temperature coefficient (IDS decreaes with temperature).

Why so ? Any fundamental reason or just fabrication effect ?

-CA

Title: Re: PMOS and NMOS temperature coefficient
Post by raja.cedt on Jul 18^th, 2009, 1:10am

i don't think so..have you used same bias in both cases?

Title: Re: PMOS and NMOS temperature coefficient
Post by cmos.analogvala on Jul 21^st, 2009, 12:50pm

Yes same bias voltage in both the case VGS=VDS=Vdd/2 ...The transistor is biased in saturation region ...I found it in 180nm and 90nm technologies .. I am using foundry specified model files ..

by fast i mean dc drain current increases ...i have not looked at transient results ..

The point is that it is well known that mobility degrades with temperature ..but |vt| decreases with temperature .. mobility coefficient is T^(3/2) hence mobility degrades much rapidly that |vt | decrease ..... but the results are DSm technologies are astonishing ..

Any Clue ?

-CA