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Design >> High-Speed I/O Design >> DDR3 circuit design references
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Message started by jiesteve on Jul 28^th, 2009, 1:37am

Title: DDR3 circuit design references
Post by jiesteve on Jul 28^th, 2009, 1:37am

Hi,

I will be working soon on DDR3 I/O circuits...Could you suggest some good starting references for DDR3 and/or high-speed I/O design in general?

Thanks!

Title: Re: DDR3 circuit design references
Post by neoflash on Oct 5^th, 2009, 12:58pm

DDR3 is mostly custom design and doesn't have much publications on it.

Be prepared to search for DLL, phase interpolator.

Title: Re: DDR3 circuit design references
Post by jiesteve on Nov 5^th, 2009, 10:20am

I'm working on the ZQ calibration circuit. If I'm reading the spec correctly, the circuit needs to be capable of sensing a 0.5% change in output driver impedance. Translated into a deltaV I calculate this to be 1.8mV at the input of the comparator. This means I need to design the comparator to have an offset voltage =1.8mV (say over 3sigma) or does it need to be less, say half that?

If it's half that, then I need to burn 4x the power and spend 4x more area on the comparator. I'm thinking it's OK to design it to be =1.8mV over 3sigma... is my thinking wrong here?

Title: Re: DDR3 circuit design references
Post by SacY on Nov 17^th, 2009, 5:16am

Jiesteve,
Before I comment on anything can you please let me know how you calculated 1.8mv. Because as per DDR3 spec the deltaV = (vdd/2) * 0.5%
which will come around 3.75 mV as vdd will be 1.5V as per standard.

Title: Re: DDR3 circuit design references
Post by jiesteve on Nov 24^th, 2009, 7:28pm

Hi SacY,

The DDR3 spec calls for the ZQ circuit to be sensitive to 0.5% of _RZQ=240 ohms_

This is how I calculated deltaV:

Taking VDD=1.5v: (find voltage change with 0.5% change in driver resistance:

V = ( 240*(1.005) / 240 + 240*(1.005) ) * VDD

Then take the difference from midpoint 1.5/2 = 750mV.

Title: Re: DDR3 circuit design references
Post by pavanspai on Jan 10^th, 2010, 10:44pm

Hi ,

I am working on ZQ calibration of DDR3 , according to electrical characteristics of ODT/Driver impedance can very +/- 10% .

But the short calibration is capable of correcting the impedance error up to 0.5% . And calibration interval calculated with this as reference , will always run whenever impedance falls out of the impedance error limit.
That means impedance always will be calibrated to +/- 0.5% .

In such case why the electrical specs allows +/-10% variation ?