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Design Languages >> VHDL-AMS >> Capacitor model
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Message started by ankit12 on Jul 28^th, 2009, 6:33am

Title: Capacitor model
Post by ankit12 on Jul 28^th, 2009, 6:33am

Hi,

I wanted to model a capacitor which has series resistance, inductance also and these value changes w.r.t temperature and bias voltage.

But I am encountering the following errors for "IF-THEN" statements,

library IEEE;
library EDULIB;
use IEEE.ELECTRICAL_SYSTEMS.all;
use IEEE.THERMAL_SYSTEMS.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Cap_model is

generic (
cap: CAPACITANCE := 471.0;
temp: TEMPERATURE := 0.0; -- Temperature @ 25C,125C & -55C
v_b: VOLTAGE := 0.0 -- Bias Voltage @ 0V,25V,50V,75V and 95V
);
port (
terminal p1: ELECTRICAL;
terminal p2: ELECTRICAL
);

end entity Cap_model;

architecture default of Cap_model is
TERMINAL V_IN: ELECTRICAL;
TERMINAL V_RES2: ELECTRICAL;
TERMINAL V_MID: ELECTRICAL;
TERMINAL V_RES: ELECTRICAL;
TERMINAL V_RES1: ELECTRICAL;
ALIAS ground is ELECTRICAL_REF;

begin

if temp = '25.0' and v_b = '0.0' then

C1: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.00000000046521)
port map (p1 => V_RES,p2 => ELECTRICAL_REF);

C2: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.0000000000065)
port map (p1 => V_RES2,p2 => ELECTRICAL_REF);

R1: entity EDULIB.resistor(ideal)
generic map (res => 1850.0)
port map (p1 => V_RES1,p2 => V_RES);

R2: entity EDULIB.resistor(ideal)
generic map (res => 562.69)
port map (p1 => V_RES2,p2 => V_MID);

L1: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000041)
port map (p1 => V_MID,p2 => V_IN);

L2: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000779)
port map (p1 => V_RES,p2 => V_MID);

elsif temp = '-55.0' and v_b = 25.0 then

C1: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.00000000040123)
port map (p1 => V_RES,p2 => ELECTRICAL_REF);

C2: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.0000000000065)
port map (p1 => V_RES2,p2 => ELECTRICAL_REF);

R1: entity EDULIB.resistor(ideal)
generic map (res => 6300.0)
port map (p1 => V_RES1,p2 => V_RES);

R2: entity EDULIB.resistor(ideal)
generic map (res => 1800.00)
port map (p1 => V_RES2,p2 => V_MID);

L1: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000041)
port map (p1 => V_MID,p2 => V_IN);

L2: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000779)
port map (p1 => V_RES,p2 => V_MID);

end if;

end architecture default;

Please find the errors that I am encountering,

Compiling Entity Declaration CAP_MODEL
Compiling Architecture DEFAULT of CAP_MODEL
-------------------
35: if temp = '25.0' and v_b = '0.0' then
^^^
[Error] Missing ending "'"
-------------------
35: if temp = '25.0' and v_b = '0.0' then
^^
[Failure] Syntax error : received '.'
while expecting 'generate'
or 'use'

ENTITY CAP_MODEL deleted
Invalid design unit: DEFAULT/CAP_MODEL
Compiled object not created due to errors

Please let me know on how to proceed, or what is that i am doing wrong.

Regards,
Ankit

Title: Re: Capacitor model
Post by Geoffrey_Coram on Aug 11^th, 2009, 10:14am

You might need to post this in the VHDL-AMS section, since it looks like a syntax problem with your code, not a modeling question.

Title: Re: Capacitor model
Post by Andrew Beckett on Aug 19^th, 2009, 4:15am

Two problems:

1. You have used quotation marks around floating point numbers in these parts:

Code:

if temp = '25.0' and v_b = '0.0' then

2. Conditional instantiation needs to be done with generate clauses rather than if then else statements.

Note I'm not particular VHDL literate, but from a quick look at a VHDL book and some testing in AMS Designer (I think you're using something different) I can get it to compile with:

Code:

library IEEE;
library EDULIB;
use IEEE.ELECTRICAL_SYSTEMS.all;
use IEEE.THERMAL_SYSTEMS.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Cap_model is

generic (
cap: CAPACITANCE := 471.0;
temp: TEMPERATURE := 0.0; -- Temperature @ 25C,125C & -55C
v_b: VOLTAGE := 0.0 -- Bias Voltage @ 0V,25V,50V,75V and 95V
);
port (
terminal p1: ELECTRICAL;
terminal p2: ELECTRICAL
);

end entity Cap_model;

architecture default of Cap_model is
TERMINAL V_IN: ELECTRICAL;
TERMINAL V_RES2: ELECTRICAL;
TERMINAL V_MID: ELECTRICAL;
TERMINAL V_RES: ELECTRICAL;
TERMINAL V_RES1: ELECTRICAL;
ALIAS ground is ELECTRICAL_REF;

begin

G1: if temp = 25.0 and v_b = 0.0 generate

C1: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.00000000046521)
port map (p1 => V_RES,p2 => ELECTRICAL_REF);

C2: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.0000000000065)
port map (p1 => V_RES2,p2 => ELECTRICAL_REF);

R1: entity EDULIB.resistor(ideal)
generic map (res => 1850.0)
port map (p1 => V_RES1,p2 => V_RES);

R2: entity EDULIB.resistor(ideal)
generic map (res => 562.69)
port map (p1 => V_RES2,p2 => V_MID);

L1: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000041)
port map (p1 => V_MID,p2 => V_IN);

L2: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000779)
port map (p1 => V_RES,p2 => V_MID);

end generate ;

G2: if temp = -55.0 and v_b = 25.0 generate

C1: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.00000000040123)
port map (p1 => V_RES,p2 => ELECTRICAL_REF);

C2: entity EDULIB.capacitor(Ideal)
generic map (cap => 0.0000000000065)
port map (p1 => V_RES2,p2 => ELECTRICAL_REF);

R1: entity EDULIB.resistor(ideal)
generic map (res => 6300.0)
port map (p1 => V_RES1,p2 => V_RES);

R2: entity EDULIB.resistor(ideal)
generic map (res => 1800.00)
port map (p1 => V_RES2,p2 => V_MID);

L1: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000041)
port map (p1 => V_MID,p2 => V_IN);

L2: entity EDULIB.inductor(Ideal)
generic map (Ind => 0.000000000779)
port map (p1 => V_RES,p2 => V_MID);

end generate;

end architecture default;

(well, I didn't have the sub-cells, but it got rid of all the other errors, which were very similar to the errors you were seeing).

Note doing = comparisons on real numbers is never a good idea, although I guess these are likely to be literal values, so may be OK.

Regards,

Andrew.