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Design >> High-Speed I/O Design >> cmos i/o driver design
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Message started by phani on Aug 5th, 2009, 12:09am

Title: cmos i/o driver design
Post by phani on Aug 5th, 2009, 12:09am

Hello all, I am new here.

I want to know how a cmos i/o driver is designed for the given current specs and max. on resistance.

it would be better if any body can explain the design procedure also using spice.

Thanx,
Phani.

Title: Re: cmos i/o driver design
Post by raja.cedt on Aug 5th, 2009, 1:22am

hi,
  i think nobody will give both..generally they give termination resistance at the driver....first you have to see how much swing your RX can detect and how much signal attenuation in channel...sum of these two will give the driver swing.....this swing is the drop across the termination resistance......

Thanks,
Rajasekhar.

Title: Re: cmos i/o driver design
Post by phani on Aug 5th, 2009, 3:35am

yes you r correct,

If you see in case of SSTL min. Ioh and Iol are required so that min levels are provided to the RX after channel noise and max. ron is used to terminate the line.

In this case how to design the driver to meet Ioh and Iol and ron values.

Title: Re: cmos i/o driver design
Post by raja.cedt on Aug 5th, 2009, 9:42am

hi,
   i didn't understand your terminology (like ioh,iol)..could you please explain?

thanks,
rajasekhar.

Title: Re: cmos i/o driver design
Post by phani on Aug 27th, 2009, 1:51am

Ioh and Iol are source and sink currents respectively.
JEDEC standard says to source and sink some minimum currents to meet the desired Vol and Voh values.

Title: Re: cmos i/o driver design
Post by ywguo on Sep 9th, 2009, 8:45pm

Hi Phani,


Quote:
Posted on: Aug 27th, 2009, 1:51am
Ioh and Iol are source and sink currents respectively.
JEDEC standard says to source and sink some minimum currents to meet the desired Vol and Voh values.  


Although I have not read JEDEC standard on SSTL. It seems that the answer is already in your own post. Just keep Ioh and Iol large enough to meet the minimum voh and maximum vol. :)


Yawei

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