The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> RF Design >> Choosing varactor polarity in LCVCO
https://designers-guide.org/forum/YaBB.pl?num=1250204516

Message started by scv on Aug 13^th, 2009, 4:01pm

Title: Choosing varactor polarity in LCVCO
Post by scv on Aug 13^th, 2009, 4:01pm

I am using a nmoscap_25 in TSMC for a 10G LCVCO. However, when I flip the polarity of the varactor there is an immediate degradation of phase noise (about 2~3dBc/hz at 1Mhz) although the oscillation freq is the same. I have a Vdiff between terminals of around 0 Volts since Vout_cm and Vtune are the same. The case where I connect the gate to the core and source/drain terminals to vtune (DC voltage) gives me the better phase noise.

Any inputs on the same? Thanks.

Title: Re: Choosing varactor polarity in LCVCO
Post by Read_MLY on Aug 19^th, 2009, 2:38am

why don't you use pmoscap?I think the polarity of nmoscap affects your phase noise because different polarity has different Kv(dC/dV),when Kv is small, phase noise is better,when Kv is larger,phase noise is worse.

but,when you simulate your circuit, how much parasitical capacitance which is caused by layout line and test bench? :)

Title: Re: Choosing varactor polarity in LCVCO
Post by scv on Aug 21^st, 2009, 4:37pm

Hi,

I didn't use pmoscap_25 since the PDK doesn't have a varactor cell for the same. I could have used transistors instead but wasnt sure if the dedicated varactor cell was modeled any better.

I had initially assumed that the issue was the Kvco. However, this discrepancy in phase noise exists even when I have the same Kvco in both cases. And this wasn't a post layout simulation. So there isn't any parasitics in the picture.
thanks.

Title: Re: Choosing varactor polarity in LCVCO
Post by kataria0 on Aug 22^nd, 2009, 8:49am

Hi SCV
Trying to understand your ckt better:
It seems like you first tried a varactor, and also tried flipping its polarity and noticed Phase Noise degradation?
You then also tried some MOSFET as you mention drain/source terminals?

You could post an image of your portion of the circuit to avoid any confusion. You may download IrfanView to capture image and save it as JPEG and then attach that here.

I look forward to hearing in regard to this. Phase Noise issues interest me a lot. :)

Title: Re: Choosing varactor polarity in LCVCO
Post by depend135 on Sep 1^st, 2009, 6:58am

i think it's because of the parastic well capacitor and the bulk resistor that exist in the source/drain terminal.If the source/drain connet to the core, the parastic cap and res will decrease the effective Q of the LC tank, as a result, phase nosie performance will be affected. If the gate terminal connect to the core, vtune is the virtual ground ,so the parastic cap and res are shaded , the LC tank Q is larger.