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Design Languages >> Verilog-AMS >> can Verilog-A model run unix command?
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Message started by seefree on Oct 7^th, 2009, 1:20pm

Title: can Verilog-A model run unix command?
Post by seefree on Oct 7^th, 2009, 1:20pm

I want to run Unix command during simulation, e.g, spectre or other simulators follows the netlist file. Can I write a veriloga model which could execute some unix commands, such as env, cp, pwd, etc?

Thanks,

Title: Re: can Verilog-A model run unix command?
Post by Geoffrey_Coram on Oct 8^th, 2009, 6:10am

No.

Title: Re: can Verilog-A model run unix command?
Post by Andrew Beckett on Jan 6^th, 2010, 11:56am

Not VerilogA, but spectre has a "shell" analysis which would allow you to do this.

Type "spectre -h shell" to see the details.

For example:

Code:

doCmd shell cmd="cp file1 file"

Regards,

Andrew.

Title: Re: can Verilog-A model run unix command?
Post by cmolsen on Feb 20^th, 2011, 12:22pm

One year later now... Is it still impossible to run unix commands in Verilog-A?

If so, what is the reason this is not being made possible to do?

Can individual tool vendors like Cadence and Synopsys enable such functionality in their versions of Verilog-A ?

---Michael Olsen

Title: Re: can Verilog-A model run unix command?
Post by Geoffrey_Coram on Feb 22^nd, 2011, 5:26am

Verilog-AMS is a hardware description language; by design, it is intended to be simulator-independent (and operating-system independent).

I don't know why you expect that this feature would be appropriate for a modeling language.

Title: Re: can Verilog-A model run unix command?
Post by Marq Kole on Feb 24^th, 2011, 6:03am

Maybe more specifically: what did you have in mind for unix commands to run? There might be alternative ways to achieve the same end result without having to resort to unix commands from inside a model...

Cheers
Marq

Title: Re: can Verilog-A model run unix command?
Post by cmolsen on Feb 25^th, 2011, 9:09am

For example, I thought it could be useful to notify my iPhone about the progress of a time consuming Verilog-A simulation.

A little monitor function inside the VA module examines internal conditions, e.g. time or some local state. When some condition is met, it prints out relevant internal variables to a file. It then uses the system() command to call a network application that sends a message to an email address or to my "Verilog-A" iPhone app from which I may even be able to control the operation of the VA module, like terminating it or adjusting variables.

I can understand there are dangers associated with a VA module taking external input. But such is life with most programming languages. Why do we need special protection when it comes to Verilog-A?

---Michael

Title: Re: can Verilog-A model run unix command?
Post by cmolsen on Feb 25^th, 2011, 3:37pm

Geoffrey_Coram wrote on Feb 22^nd, 2011, 5:26am:

When I use the fopen() command in VA, isn't the VA interpreter interacting with the OS or does it channel the fopen() command through the simulator interface?

My guess is the VA interpreter interacts with the OS to open the file. And if it can do that then it could probably also handle any other OS function call, like system().

The VA code itself would still be OS independent. It's the interpreter that has to be deal with the OS. But maybe I have it all mixed up.

Title: Re: can Verilog-A model run unix command?
Post by Marq Kole on Feb 28^th, 2011, 12:45am

This appears to me like a problem that should not be solved in Verilog-A. A much better solution that can be done completely in the OS is to have a background process watch a certain file or location for new files or updates of existing files. Then upon noting any such change at the monitored location the process can (re)read the updates and base its actions on the new information.

This is not a specifically analog feature so it will not be taken up by the Accellera Verilog-AMS standardization: it should be part of the larger IEEE 1800 standard. Unless you are willing to spend a lot of time lobbying and convincing people at the IEEE 1800 standardization group - and I personally don't think you have a very strong use case - there is not going to be a system() call in Verilog-A.

Cheers,
Marq