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Measurements >> Phase Noise and Jitter Measurements >> Jitter Measurements in a Phase Locked Loop
https://designers-guide.org/forum/YaBB.pl?num=1255003668

Message started by Mayank on Oct 8^th, 2009, 5:07am

Title: Jitter Measurements in a Phase Locked Loop
Post by Mayank on Oct 8^th, 2009, 5:07am

Hi,
I am confused as to when do we perform Time-Domain Phase Noise (which cadence calls 'Time-Domain' in Pnoise analysis)Analysis and when to perform Single-Side Band (which cadence calls as 'Sources' in pnoise analysis) Analysis ?
Like for VCO, we generally use sources PNOISE analysis and for Loop Divider, we opt for Time-Domain PNOISE analysis. Can somebody pls. tell why so ??
I am given to understand that Time domain phase noise gives Edge-to-Edge Jitter while SSB/DSB Phase Noise gives Cycle-Cycle OR Period Jitter.
Is this statement correct ??

Also, what is the exact difference between Edge-to-Edge Jitter and Period Jitter ? Cadence explains it in one of its Application Notes but i didnt understand the exact difference. I am still very confused because any noise on one edge will cause noise in the period of that cycle also. Pls. elaborate more on this.

regards,
Mayank.

Title: Re: Jitter Measurements in a Phase Locked Loop
Post by raja.cedt on Oct 8^th, 2009, 8:19pm

hi i donno about simulation in cadence but for the theoretical concepts regarding jitter you can use the following reference's.

http://www.ee.ucla.edu/~brweb/papers/Journals/H&RTCas99.pdf
http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

thanks,
Rajasekhar.

Title: Re: Jitter Measurements in a Phase Locked Loop
Post by Mayank on Oct 8^th, 2009, 9:09pm

Hi raja,
Thanx for the material.

mayank.

Title: Re: Jitter Measurements in a Phase Locked Loop
Post by Mayank on Oct 11^th, 2009, 7:03am

Hi all,
I have done some further reading on the subject...I have drawn a few conclusions :--

1. In case of blocks that are driven by an input clock(eg. dividers),ie the output transition in dependent on the input transition, we measure Edge-to-Edge Jitter Jee.

2. In case of blocks in which transitions of the output are important (eg. dividers whose o/p goes to PFD) , we measure Jitter through time-domain(time-strobed) PNOISE Analysis.

3. In case of blocks in which an output transition is dependent on previous OUTPUT transition, we measure Period Jitter.

4. CYCLE-to-CYCLE Jitter is the maximum Jitter possible assuming complete un-correlated behaviour. PERIOD JITTER,on the other hand, includes some effect of correlation of noise,thereby decreasing jitter.

Pls educate me :- Are all of these statements correct ??

regards,
Mayank.

Title: Re: Jitter Measurements in a Phase Locked Loop
Post by Mayank on Oct 11^th, 2009, 7:14am

Hi everyone,

One more question;
when PLL is in a Locked State, which one indicates the maximum jitter possible at PLL output -- PERIOD JITTER OR CYCLE-to-CYCLE JITTER ??

Is it that cycle-to-cycle jitter Jcc is relevant when PLL is still not locked but is in the process of locking ? After Locking is done, PERIOD Jitter Jc is the one which is the actual measure of Jitter at PLL o/p.

--Mayank.

Title: Re: Jitter Measurements in a Phase Locked Loop
Post by raja.cedt on Oct 19^th, 2009, 5:51am

hi Mayank,
even i don't have much command, still i will try deliver what i know...While locking don't think about jitter because during locking to its frequency period keep on changing from cycle to cycle and there you can't define even mean period. So jitter is always measured in lock condition. During locking cycle to cycle jitter is high due low pass filter action of the filter. But generally in plls everybody used to measure random jitter and deterministic jitter. Even though the many jitter components are defined all our high end CRO's gives convolved version of those.

Thanks,
rajasekhar.