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Simulators >> Circuit Simulators >> simulating snapback elements with spectre
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Message started by vivkr on Oct 16^th, 2009, 8:00am

Title: simulating snapback elements with spectre
Post by vivkr on Oct 16^th, 2009, 8:00am

I am trying to simulate a circuit containing a snapback protection element to check the ESD robustness level.

As snapback elements present a negative impedance, the simulator (Spectre) has trouble converging. The simulation ends abruptly shortly after the onset of snapback with the simulator citing convergence difficulties.

As I am not allowed to modify the model, I am trying to see what the best simulator settings should be and check if convergence is achievable under these. The following is what I have tried and I would be glad to have some more tips:

1. Sim settings relaxed to liberal

2. Gmin raised to 1e-9. This larger value should still be acceptable.

3. Hunted down nodes where I get a problem with the Jacobian and tried to add (wherever possible) a large resistor in || although Gmin should do this.

4. Integration method changed to "gear2only". This is a bit of guesswork as I am not sure whether this really will help. I just expect that any tendency to ring might be suppressed like this.

Regards,

Vivek

Title: Re: simulating snapback elements with spectre
Post by boe on Oct 16^th, 2009, 9:05am

Vivek,
Have you tried adding L's and C's to ensure that any changes in current and voltage are continuous?
BOE

Title: Re: simulating snapback elements with spectre
Post by vivkr on Oct 19^th, 2009, 12:45am

boe wrote on Oct 16^th, 2009, 9:05am:

Vivek,
Have you tried adding L's and C's to ensure that any changes in current and voltage are continuous?
BOE

Unfortunately, I cannot change the problem element which is the snapback. However, your suggestion of adding a series L might be helpful.

In the meantime, I was able to add large resistors in || to the elements (around 1 MOhm) and achieve convergence, albeit still with a very slow simulation, and of course, it is not 100% clear whether the results are still sufficiently accurate.

I would have expected so since the added resistors are too large to permit any significant ESD current to flow through them, but the results seem a bit different.

Regards,

Vivek

Title: Re: simulating snapback elements with spectre
Post by Ken Kundert on Oct 19^th, 2009, 12:44pm

Personally I would not mess either with gmin or adding parallel resistors. Clearly if they are large enough to effect convergence, they are changing the behavior of the circuit.

If you are simulating with real transistor models, ones with capacitors, then the capacitors should allow you to simulate your circuit. Indeed this is the way relaxation oscillators work.

If your models do not have capacitors, and you cannot add them, then you can try adding cmin to the transient analysis. But be careful with cmin if you are adding inductors. You can inadvertently create a very high-Q resonator that causes the simulation to run slowly.

-Ken

Title: Re: simulating snapback elements with spectre
Post by vivkr on Oct 20^th, 2009, 2:12am

Thanks for that tip Ken!

Indeed, I do not like to mess with models in this manner. Indeed, the behavior is different than expected pointing out the risk of tinkering with models in this manner.

Unfortunately, the model I have is not transistor-based but coded in Verilog-A, and as models go, it is a bit too simple accounting for no parasitics and not including any intrinsic delay mechanisms. Looks like the person in charge has to make a fix.

Vivek

Title: Re: simulating snapback elements with spectre
Post by cmos.analogvala on Dec 6^th, 2009, 8:31am

You can still give cmin with initial conditions in verilog A. Have tried this one ?
-CA