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Design >> Mixed-Signal Design >> Metal width consideration for layout
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Message started by rampat on Oct 27^th, 2009, 7:16am

Title: Metal width consideration for layout
Post by rampat on Oct 27^th, 2009, 7:16am

Hi All,

In one of the switched cap circuit,I need to decide metal width for the signal paths depending on the current. i am not sure whether to consider peak current or average current for fixing the metal width.
I need to take take care of EM as well as IR considerations.
Attached image shows the simulated current profile in on the signal path.
Can some one tell me how to decide metal width w.r.t current waveform attached ?

Thanks
rampat

Title: Re: Metal width consideration for layout
Post by rampat on Oct 27^th, 2009, 7:22am

Sry I forgot to attach image file

Here it is ....

Title: Re: Metal width consideration for layout
Post by loose-electron on Oct 27^th, 2009, 9:09am

The problem is one of tolerable limits.

Max resistance - what will simulations tell you is tolerable in both max L and max R in the interconnect.

Min resistance/inductance - for present placements of components, whats the lowest resistance interconnect tht can be placed?

If you can get an interconnect in place between those two you should be fine.

Also, make a check of you contact resistance and via resistance. These can be significant.

Generally, its not too much of a problem, until you are dealing with high current circuits (amperes of current on the chip) Or high frequencies (100MHz, 60GHz, etc.), where the RLC of the network becomes critical.

Title: Re: Metal width consideration for layout
Post by Berti on Oct 28^th, 2009, 12:52am

Rampat,

Concerning electromigration the average current needs to be considered.
AC currents sometimes even have a "healing" effect on the metal wire.

Cheers

Title: Re: Metal width consideration for layout
Post by rampat on Oct 28^th, 2009, 2:12am

Hi Berti,
Can you please elaborate on "healing" effect due to AC currents on metal wire.

thanks
rampat

Title: Re: Metal width consideration for layout
Post by loose-electron on Oct 28^th, 2009, 9:54am

Berti - His currents are max of 633uA I really doubt electromigration is going to be an issue. - Jerry

Title: Re: Metal width consideration for layout
Post by Berti on Oct 29^th, 2009, 4:53am

Rampat, electromigration is the transport of material caused by the gradual movement of ions. AC currents sometimes even help to bring back some of the displaced material which basically helps to "heal" the metal wire. Unfortunately I don't remember the book I read this (there were also pictures for illustration).

Jerry, I fully agree with you. But it was part of the original post:

Quote:

...are of EM as well as IR considerations.

Regards

Title: Re: Metal width consideration for layout
Post by loose-electron on Oct 29^th, 2009, 4:46pm

Ah, ok, that makes sense - but then -
EM = electromigration
EM = electromagnetic.

I sort of ignored that.

Title: Re: Metal width consideration for layout
Post by Berti on Oct 30^th, 2009, 8:04am

:D That's the problem with abbreviations, they are ambiguous, I am also not sure what Rampat actually means with EM :)

Title: Re: Metal width consideration for layout
Post by loose-electron on Oct 30^th, 2009, 8:45am

Abrev? thts ng cuz we dnt no wht 2 say bt thm
k?
ttyl,
j

;D

if you read the above with0ut thought, you spend too much time doing one of 3 things:
texting on a cell phone...
internet chat rooms...
morse code....
pick one...

Title: Re: Metal width consideration for layout
Post by rampat on Nov 1^st, 2009, 8:17pm

Hi Berti,

For EM i meant Electro migration
Sry I did not know that will create confusion

rampat

Title: Re: Metal width consideration for layout
Post by Mayank on Nov 5^th, 2009, 2:36am

Hello folks,
Sorry for bringing this up again....But i have a similar query....

@ berti : You explained AC signals have a healing effect on interconnects....But what concerns me is --> Wont a high current spike burn off the interconnect(because of interconnect resistance) if it's not sized to carry that much current ?? What decides this size ?? ----- EM rules of some process DRM ??

In this case, i agree with the replies that the highest current spike of 630uA is not of a big concern.....But what if you design your wire for say, 1mA avg current, but peak current spikes of 2mA occur on it ??

--mayank.

Title: Re: Metal width consideration for layout
Post by loose-electron on Nov 5^th, 2009, 9:56am

95% of the time the geometry of the interconnect is dictated by the acceptable IR drop.

Lots of current, and little allowable IR loss in the wire, means wide interconnects to keep the R down.

Its usually not much more complicated than that.

Foundry may or may not have a set of current density rules for metal interconnects also.

RF design is a different game (line inductance becomes an issue as frequencies get higher, I generally dont worry about L of the lines inside until I hit 500MHz or so.)

Electromigration rules will be unique to the foundry as well.