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Message started by rampat on Nov 2^nd, 2009, 12:44am

Title: Future analog design trends
Post by rampat on Nov 2^nd, 2009, 12:44am

Hi All

what will be the future of analog design for next 15-20 years ..What kind of circuit skills designer should develop for upcoming future technologies ?

rampat

Title: Re: Future analog design trends
Post by vivkr on Nov 3^rd, 2009, 3:44am

Hi Rampat,

It is always risky to predict the future. However, the following things are likely to keep analog designers busy:

1. Ever faster operating speed requirements.
2. Ever tighter power consumption constraints.
3. Ever higher levels of integration, eliminating external components.
4. Increasing amount of on-chip sensors and need to drive these => more data converters, on-chip dc-dc converters/power management.

If you wish to prepare for the future, then you would do well to sharpen your understanding of the fundamental concepts. That would allow you to work in about any field, provided that you are motivated enough.

Regards,

Vivek

Title: Re: Future analog design trends
Post by emad on Nov 28^th, 2009, 12:57am

Here are my two cents:

Analog designers ought to know a lot more signal processing for system architectures. They need to understand statistics a bit more because the term process-corners will eventually vanish in favor of custom-made process variability limits. There will always be need for understanding device physics to a reasonable degree but this has always been there.

-Emad

Title: Re: Future analog design trends
Post by RFICDUDE on Dec 15^th, 2009, 8:38pm

What are "custom made variability limits"???

In my experience the variability never gets any better. It is the circuit that must fit within the variability and still meet the expected performance. It is up to the engineer to argue or determine what performance variation is reasonable given the variability of a specific process.

I tend not to rely on Monte Carlo for absolute performance. I simply don't have time to let 100+ simulations run just to find a deficiency in my design. Corner simulations help find fatal errors while Monte Carlo helps with yield analysis.

But I must say that Monte Carlo is very valuable for mismatch analysis; although, I have always wanted a way to run Monte Carlo where the mismatch parameters simply toggle randomly +/- between some worst case or specified deviation (maybe 2-3 sigma) just to quickly reveal the true mismatch sensitivities in the circuit

Title: Re: Future analog design trends
Post by love_analog on Apr 23^rd, 2010, 6:48am

Another thing I'd like to add is that they will need to understand more about RTL and digital flows.
As we move into bigger and bigger SoCs, there will be more and more programmability and more and more digital sequences to follow (eg power up, reset etc).
For instance, We will need to get used to PLLs being modeled as pure RTL vs just verilogA so as to not bog down the whole SoC verification flow.