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Design >> Mixed-Signal Design >> Generate a Phase Shifted Clock
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Message started by bhavuli on Dec 22^nd, 2009, 12:23pm

Title: Generate a Phase Shifted Clock
Post by bhavuli on Dec 22^nd, 2009, 12:23pm

Hi Folks,

Does anyone know a simple way (using digital logic) that has an input a periodic clock and the outputs are:

(1) a 180 degree phase shifted clock

(2) a 0 degree phase shifted clock so that it is in phase with (1).

Thanks!

Title: Re: Generate a Phase Shifted Clock
Post by raja.cedt on Dec 22^nd, 2009, 8:22pm

hi,
use DLL which can give better phase accuracy or else if you have any phase interpolator get the corresponding code to get desired pahse delay.

Thanks,
Rajasekhar.

Title: Re: Generate a Phase Shifted Clock
Post by loose-electron on Dec 22^nd, 2009, 9:49pm

yeah it's called an inverter...

If the phase accuracy isn't critical one inverter and you are done. If the problem is more demanding than that, you need to specify a bit more what you want.

Title: Re: Generate a Phase Shifted Clock
Post by raja.cedt on Dec 23^rd, 2009, 4:46am

hi,
you have specify how much ppm of shift you can tolerate across monte..otherwiese presise 180 how you will get?

Thanks,
Rajasekhar.

Title: Re: Generate a Phase Shifted Clock
Post by analog_rf on Dec 26^th, 2014, 3:44am

I know this is an old post. Iam currently trying to generate a mult phase clock. Trying to us a PI (two inverters with output shorted).Any help on how to go about trimming this?My clock frequency is 2G.Currently able to reach 5ps within target across process and 5ps across monte.Any help will be appreciated.

Title: Re: Generate a Phase Shifted Clock
Post by loose-electron on Jan 19^th, 2015, 1:29pm

create a frequency multiplier PLL and reference it to a lower frequency crystal.

Title: Re: Generate a Phase Shifted Clock
Post by RobG on Feb 10^th, 2015, 6:59pm

loose-electron wrote on Dec 22^nd, 2009, 9:49pm:

yeah it's called an inverter...

Ha, that is what I was thinking. In addition, to line up the non-inverted signal run it through an "on" t-gate with the same sized devices as the inverter. See figure 12.18 of the switched cap chapter of Razavi's book.

When I first saw it I figured it was an horrible hack, but it actually works well to align the clock and clock-bar signals. Not sure if it will get you 5 ps, but it is a trick worth remembering to get you close. I suppose you could trim the tgate delay by trimming the gate drive. I don't understand the PI cricuit described by analog_rf.

Title: Re: Generate a Phase Shifted Clock
Post by loose-electron on Feb 15^th, 2015, 1:56pm

For the 2G frequency mentioned I would suggest getting complementary signals directly off of the oscillator. Most structures can create a CK, N_CK scenario at the inverter.

Title: Re: Generate a Phase Shifted Clock
Post by Mehdi Abderezai on Feb 24^th, 2015, 11:25am

I use cross coupled differential circuit, you can invert the input and delay match it with a TGate to drive the two diffpair inputs, then buffer out the output. Parasitic matching in important in your layout, also fast rise and fall time with weak load devices in your diff.

Duty Cycle might get F-ed up tho. but you will be almost 100% phase shifted at 0 and 180 with the two outputs.