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Design >> Analog Design >> design example for gm/Id methodology
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Message started by ipyd on Dec 30^th, 2009, 2:41am

Title: design example for gm/Id methodology
Post by ipyd on Dec 30^th, 2009, 2:41am

hi all..

i have read that gm/Id methodology is useful for designing CMOS analog circuit in every operating region. but i am still confused when trying to design simple telescopic differential op-amp.

i have known how to plot every graph that is used in this methodology, for instance gm/Id vs. Id/(W/L) graph ..

but i am confused about how to use that graph to find size of W and L of transistors..

i have googled for some literatures or tutorial that explain about how to design using this methodology step-by-step.. unfortunately, i haven't found any yet..

does anyone have it?
i think i should read more..

thank you

Title: Re: design example for gm/Id methodology
Post by chmf on Dec 30^th, 2009, 5:16pm

You can refer EE240 project.
I'm studying gm/id methodology, but do not know how to build the test bench in order to simulate open-loop gain Vs vod, AC loop gain @Vod=0v and AC loop gain @Vod=Vod,max.

Hope someone can give some helps.

Title: Re: design example for gm/Id methodology
Post by Mayank on Dec 30^th, 2009, 8:44pm

Hi guys,
Go through Borris Murmann's EE 240 course..[esp. lec 3 4 5]....It explains gm/id quite extensively.....It would surely help.

@ chmf : I mailed you on gmail....Did that help ??

regards,
Mayank.

Title: Re: design example for gm/Id methodology
Post by ipyd on Dec 31^st, 2009, 1:16am

Mayank wrote on Dec 30^th, 2009, 8:44pm:

Go through Borris Murmann's EE 240 course..[esp. lec 3 4 5]....It explains gm/id quite extensively.....It would surely help.

Didn't find any Murmann's EE240, but his EE214 instead.
Thanks anyway..

Title: Re: design example for gm/Id methodology
Post by Mayank on Dec 31^st, 2009, 7:29am

Ohhh My bad,

It's EE214 indeed....Advanced Analog Integrated Circuit Design. https://ccnet.stanford.edu/cgi-bin/course.cgi?cc=ee214&action=main_page

--
regards,
Mayank.

Title: Re: design example for gm/Id methodology
Post by Ken Kundert on Jan 1^st, 2010, 6:57pm

EECS240 would be the number at Berkeley, where he used to teach.

-Ken

Title: Re: design example for gm/Id methodology
Post by RFICDUDE on Jan 2^nd, 2010, 7:38pm

There is a good new book dedicated to the subject of CMOS design by length and inversion coefficient.

I highly recommend it as a reference, and it has a couple of OTA examples in the later chapters of the book.

Tradeoffs and Optimization in Analog CMOS Design, John Wiley and Sons Ltd., ISBN 978-0-470-03136-0, June 2008.

He also has a website where you can download some Excel based design example worksheets used in the book.

Title: Re: design example for gm/Id methodology
Post by nobody on Jan 2^nd, 2010, 9:56pm

I read that book and the author uses EKV model as examples.

Title: Re: design example for gm/Id methodology
Post by ipyd on Jan 3^rd, 2010, 3:48pm

it's David Binkley's book, isn't it?

Title: Re: design example for gm/Id methodology
Post by jiesteve on Jan 4^th, 2010, 7:21pm

Here's a gm/id book I've been looking at getting on amazon, it looks like it's finally out..

Has anyone obtained a copy?

Title: Re: design example for gm/Id methodology
Post by RFICDUDE on Jan 5^th, 2010, 3:46am

Yes, it is Dr. David Binkley's (UNC Charlotte) book.
The book is a comprehensive presentation on how CMOS performance parameters are related to Length and inversion coefficient with single ended and full differential OTA design examples.

However, it is not quick explanation or lecture on how to design an OTA using gm/Id. But the material could be adapted into any analog CMOS design course.

Title: Re: design example for gm/Id methodology
Post by jiesteve on Jan 7^th, 2010, 5:59pm

The link to the book I was talking about above is here:

http://www.amazon.com/Methodology-sizing-low-voltage-analog-Circuits/dp/0387471006/ref=sr_1_1?ie=UTF8&s=books&qid=1262915951&sr=8-1

Title: Re: design example for gm/Id methodology
Post by ipyd on Jan 12^th, 2010, 9:09am

i am confused how to setup simulation to get gm/ID vs ID/W graph.

in Mr.Murmann's lecture notes, he use single nmos which its drain and gate isn't connected each other. he uses about VDD/2 for VDS voltage and runs dc simulation for variable VGS voltage. FYI, I found different result for different VDS voltage.

On the other hand, in Ashutosh Tiwari's lecture notes, he also runs dc simulation for variable VGS voltage but with drain terminal connects to gate terminal, which ensure the device remains in saturation region.

which one is correct?

**please refer to : http://discovery.bits-pilani.ac.in/discipline/eee/agupta/microelectronic-circuits/spice-online/online-2/Gm_BY_ID_Methodology.pdf for Ashutosh Tiwari's lecture notes.

Title: Re: design example for gm/Id methodology
Post by Mayank on Jan 12^th, 2010, 8:54pm

Hi,
Both methods are approximation to ideal situation....

Quote:

FYI, I found different result for different VDS voltage.

Obviously, you will find different results for different vds voltages...MOS current has a loose dependence on vds too....But until the vds is too low, the change in the figures of merit of a MOS is very less.

If you want such accurate matching, sweep both VGS and VDS voltages and generate data for different vgs / vds permutations & you are good to go.

--
Mayank.

Title: Re: design example for gm/Id methodology
Post by analogrf on Jan 15^th, 2010, 5:51pm

Hi Mayank,

I had a very long discussion at edaboard, about getting the correct gm/id VS id/(W/L) curves. Problem is, ultimately i would not get the correct curves. Could u suggest a reason if you have tried this before ?
http://www.edaboard.com/ftopic377596.html

Title: Re: design example for gm/Id methodology
Post by ipyd on Jan 23^rd, 2010, 6:38am

Hi all,

in this methodology, do we also have to find the characteristic of rds of the transistor? because I find myself stuck when trying to design an amplifier with active-load in which the gain is a function of rds.

if yes, how to get the curve of it ?

Thank you

Title: Re: design example for gm/Id methodology
Post by yvkrishna on Jan 30^th, 2010, 11:26pm

hi ipyd,

see this for characterizing gds ...from ee214 lectures.

Regards,
Vamshi

Title: Re: design example for gm/Id methodology
Post by ywguo on Feb 19^th, 2010, 3:58am

ipyd wrote on Jan 12^th, 2010, 9:09am:

Hi ipyd,

I run a simple simulation, in which the drain voltage and gate voltage are swept. Gm/Id for nmos and pmos are ploted and attached here. It is 0.13um CMOS process, 1.2V nmos and pmos. Gm/Id curves keep almost constant unless VD (drain-source voltage) becomes near zero. It means that this method is applicable in almost all operating regions. So both method can get good enough results to let the designers make their choices. Please remember that such the drain-source voltage usually is not equal to the real value when the transistors are used in OPAMP and the above results are good enough.