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Design >> Analog Design >> about non-overlap clock problem
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Message started by lhlbluesky_lhl on Jan 4^th, 2010, 5:41am

Title: about non-overlap clock problem
Post by lhlbluesky_lhl on Jan 4^th, 2010, 5:41am

in many sc ciruits, two-phase non-overlap clock is usually used. here, i have some questions:

1, make a 1M clock for example (Fclk=1M), what is the time interval of non-overlap (Tnon-overlap)? what is the percentage of Tnon-overlap in Tclk (1us)?
or what is the minimum value of Tnon-overlap? how to decide the time interval of non-overlap (Tnon-overlap) for a given Tclk?

2, to realize bottom plate sampling, phi1 is usually used (phi1d and phi2d are two-phase non-overlap clock), phi1 and phi1d have almost the same rising edge, but phi1 has a earlier falling edge than phi1d (interval = Tearly). here, what is the value of Tearly? what is the percentage of Tearly in Tclk (1us)? how to decide the value of Tearly for a given Tclk?

i need some explanations, oe some related papers.
thanks all for your reply. thanks.

Title: Re: about non-overlap clock problem
Post by raja.cedt on Jan 4^th, 2010, 6:07am

hi,
those are so stright..just try from the sims..Only thing you should take care abut is whether shiwtch is completely off during that period,if so then it's fine.