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Design Languages >> Verilog-AMS >> ROM acess in VerilogA
https://designers-guide.org/forum/YaBB.pl?num=1265712619

Message started by hali on Feb 9^th, 2010, 2:50am

Title: ROM acess in VerilogA
Post by hali on Feb 9^th, 2010, 2:50am

Hi,I need help regarding ROM access in VerilogA cadence.I want to store a lookup table in ROM through VerilogA.I want to know how can i code this?or how to acess memory in verilogA? :-/

Title: Re: ROM access in VerilogA
Post by pancho_hideboo on Feb 9^th, 2010, 6:07am

hali wrote on Feb 9^th, 2010, 2:50am:

Hi,I need help regarding ROM access in VerilogA cadence.
I want to store a lookup table in ROM through VerilogA.
I want to know how can i code this?or how to acess memory in verilogA? :-/

What do you want to do ?

Do you want to use competely same ROM access in Verilog-D ?
If so, use Verilog-AMS.

If you simply want to use some table written by ascii code, use $table_model() in Verilog-A.
See http://www.designers-guide.org/Forum/YaBB.pl?num=1239903838

Title: Re: ROM acess in VerilogA
Post by hali on Feb 9^th, 2010, 12:39pm

Thanks for the reply.But actually i want to store a look up table of 8b10b coding in the rom.

Title: Re: ROM access in VerilogA
Post by pancho_hideboo on Feb 9^th, 2010, 4:37pm

Do you understand Verilog-A, Verilog-D and Verilog-AMS ?

hali wrote on Feb 9^th, 2010, 12:39pm:

But actually i want to store a look up table of 8b10b coding in the rom.

Available variables are 32bit integer and 64bit real in Verilog-A.
Simply declare array of integer.
"integer mem8b10b[0:9];"

You can write content of mem8b10b to file by "$strobe()".
You can read back content of file by "$table_model()".

Title: Re: ROM acess in VerilogA
Post by hali on Feb 11^th, 2010, 1:29am

thank u so much.You reply helped me alot. :)

Title: Re: ROM access in VerilogA
Post by pancho_hideboo on Feb 11^th, 2010, 2:05am

It seems that your application is RAM not ROM.

Both "$strobe()" and "$table_model()" are not needed.