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Design Languages >> Verilog-AMS >> verilog A code for 16:1 mux
https://designers-guide.org/forum/YaBB.pl?num=1266186403

Message started by bal on Feb 14^th, 2010, 2:26pm

Title: verilog A code for 16:1 mux
Post by bal on Feb 14^th, 2010, 2:26pm

i need a verilog A code for 16:1 mux ..thank you

Title: Re: verilog A code for 16:1 mux
Post by pancho_hideboo on Feb 15^th, 2010, 2:00am

http://www.designers-guide.org/Forum/YaBB.pl?num=1260351750/5#5

If you have Cadence Spectre, see "ahdlLib/multiplexer".

You can easily modify this code to create 16:1 Mux. Here use "case ~ endcase" statement in Verilog-A code.

Title: Re: verilog A code for 16:1 mux
Post by bal on Feb 15^th, 2010, 4:13am

since its a 16:1 i have 4 select pins which i have declared it is as input pins .. so these ports cannot be used for binary to decimal conversion in further logic .. As u told ,a case statement should be used , but before using that i need find a way such that i must covert all 4 bits to decimal value store in a variable and use it in a case statement. If u could tell me a logic for above problem i can use the case statement and select the inputs . thank you..

Title: Re: verilog A code for 16:1 mux
Post by pancho_hideboo on Feb 15^th, 2010, 4:20am

There are many methods to use binary expression for case statement.

For example, see http://www.designers-guide.org/Forum/YaBB.pl?num=1265985977

Code:

`define Nbits 4
input [`Nbits-1:0] sel;
voltage [`Nbits-1:0] sel;

parameter real Vth=1.5;
integer logic_value[0:`Nbits-1];
integer sel_value;

genvar i;

analog begin

sel_value = 0;
for(i=0; i <=`Nbits-1; i=i+1) begin
logic_value[i] = (V(sel[i]) > Vth) ? 1 : 0;
sel_value = sel_value + logic_value[i]*(1<<i);
end

case(sel_value)
.....
endcase

end

Read documents of Verilog-A surely.

Attached is an example for conventional usage of case statement.

Title: Re: verilog A code for 16:1 mux
Post by pancho_hideboo on Feb 15^th, 2010, 4:35am

Attached is another example for usage of binary data in case statement.

( (logic_value[3]==1) && (logic_value[2]==1) && (logic_value[1]==0) && (logic_value[0]==1) ) : "statement";