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Message started by ORNITORINCO on Feb 16th, 2010, 9:13am

Title: ncelab: *E, CUVPOM
Post by ORNITORINCO on Feb 16th, 2010, 9:13am

Hello everyone,

I am trying to simulate my PLL top level schematic in Cadence ADE (Analog Design Env). Along with verilog-a and spectre models devices I have a verilog-HDL sigma-delta modulator module. Being the sdm a mash 1-1-1 architecture, it embeds 3 first order modulators as building blocks plus the output noise-canceling network. Each one of these sub-blocks has an input reset port, and all these ports are tied together using a wire in the top level verilog file. The sdm block compiles and run correctly using the digital simulator ncsim and simVision.

When compiling in ADE (using ams simulator), I get the following error from ncelab:

ncelab: *E, CUVPOM (./inhl/verilog_fb/sdm_mash3/module/verilog.v,26|11): Port name 'reset' is invalid or has multiple connections.

Anyone can help with this issue?


Title: Re: ncelab: *E, CUVPOM
Post by Geoffrey_Coram on Feb 16th, 2010, 10:53am

I think we need to see more of your module definition to be able to help you.

Title: Re: ncelab: *E, CUVPOM
Post by ywguo on Apr 8th, 2010, 6:32pm


I came across the same error Yesterday. Check your schematic, symbol, rtl view. I suspected the schematic had not been check and save so that something is wrong. So I edit my symbol and confirm the pins are correct, then check and save the schematic. Great, it works.


Title: Re: ncelab: *E, CUVPOM
Post by subtr on Mar 18th, 2017, 6:08pm

I'm in a similar situation. My PLL has vams files. In fact I'm getting this error randomly. One simulation might work. I do some check and save in the same schematic it's asking. Next time it may work only if I restart the ADEL. It will again throw this error if I change some totally unrelated variable like pulsewidth of the input vpulse in the test bench. This is in fact one of the most untraceable issues I have ever come across. I have checked my port directions. Anyone has any idea of how to rectify this? I get different errors at different point of times too.

     Elaborating the design hierarchy:
   .PD_OUT_SEL(PD_OUT_SEL), .UP(up), .PHASE(PHASE_IN[31:0]),
ncelab: *E,CUVPOM (./netlist.vams,1016|43): Port name 'PHASE' is invalid or has multiple connections.

Currently it's running. I shall update the errors when I get a different one.

Title: Re: ncelab: *E, CUVPOM
Post by subtr on May 23rd, 2017, 1:30am

Does anyone have any clue about this error? I see this error at many points. There is no problem with the blocks because those blocks run perfectly with spectre. Only when they become part of the ams simulation they randomly give error. I do some random check and save, it works by chance. I don't mind the bug if there is some work around. Finally all that matters is whether we're able to simulate.

Title: Re: ncelab: *E, CUVPOM
Post by subtr on May 23rd, 2017, 2:12am

So the current situation is that, I have a working model in verilog with part A as verilog and Part B as verilog model of a delay line. I replace part B which has nothing to do with part A's code and run the ams simulation.  This results in an error relating to part A.  Part A and B being verilog runs without any problem. It would be great to know if anyone out there can help me out. If no one is able to provide a solution, there is only one way out of this : synthesize the digital and run this in spectre which will never give this illogical error.

:'( :-[

Title: Re: ncelab: *E, CUVPOM
Post by Andrew Beckett on May 28th, 2017, 2:07pm

Without seeing the data, it's pretty hard to know what's wrong, other than what the help says:

UNIX> nchelp ncelab CUVPOM
nchelp: 15.20-s022: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
ncelab/CUVPOM =
       The indicated port was either not declared in the instanced
       module, or it was mentioned too many times in the connection

Probably best thing would be to contact



Title: Re: ncelab: *E, CUVPOM
Post by subtr on Jun 2nd, 2017, 3:00pm


There is a test bench where I have two blocks with similar pin names. But they're two different instances. Just having the same name on their Reset pins, connecting the same input to both reset pins gives error. I had to go around this by creating another top level where there is one pin which connects to both through the verilog code. In fact this code with multiple connections had been running before. It started throwing this error because I replaced some other verilog model block with transistor level real block in the same test bench. If I switch it back to verilog it works. I face this error almost everywhere. I try to go around it by putting resistances in the path or having a redundant control. I really don't understand why the same input can't go to two blocks. It's perfectly normal, especially in digital. I have seen this error ONLY in illogical places and always found if I run spectre, it works like a charm. :(

Title: Re: ncelab: *E, CUVPOM
Post by AMS_ei on Jun 2nd, 2017, 9:51pm


If you have two instantiations inside the test benches and you are trying to use them with schematics, then,

1.  you have to do the following in the amsd block in an amscf.scs file:

         portmap subckt=<subckt_name>
         config inst=<instance_name> use=spice

2. Include the device model definition libraries in the amscf.scs file
3. Comment the verilog file that is compiled through irun.

Hope this helps.

Thank you.

Kind regards.

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