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Measurements >> Other Measurements >> timing and synchronization
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Message started by memomemomemo on Feb 19^th, 2010, 3:30pm

Title: timing and synchronization
Post by memomemomemo on Feb 19^th, 2010, 3:30pm

Dear all,

I have a question on BERT. (Bit Error Rate Tester). Let me tell what it is for those who want to learn.

"The bit error tester is a machine that compares a known random data pattern that is extremely long with a received (noisy) version of the sequence. Such a tester correlates a template (part of the random sequence) with the received signal and determines where the pseudorandom sequence begins. After determining this position, the PRBS tester can calculate how many subsequent bits are detected incorrectly."

And here is the Question:

What is the minimum SNR level that the BERT can really work because it needs a minimum ( BER < 10-2 ? ) to acquire lock? What is the circuit mechanism that makes the lock in very low SNR? ( such as minus 30dB)

Thanks for the help!
Mehmet

Title: Re: timing and synchronization
Post by pancho_hideboo on Feb 20^th, 2010, 12:03am

memomemomemo wrote on Feb 19^th, 2010, 3:30pm:

What is the minimum SNR level that the BERT can really work
because it needs a minimum ( BER < 10-2 ? ) to acquire lock?

It depends on bit rate.
I assume your concern is typical "Baseband Communication System Model".
About categories of "Communication System Model", see the following.
http://edocs.soco.agilent.com/display/ads2009/About+Sinks

Under ideal and optimized sampling conditions, required Es/No(=Eb/No in this case) is about 5dB for BER < 1e-2.
See http://edocs.soco.agilent.com/display/ads2009/Bit-Error-Rate+Measurement+Tutorial

About "Relationship between SNR, Es/No and Eb/No", again see the following. Here bit rate and System ENBW(Equivalent Noise Bandwidth) are required to evaluate SNR.
http://edocs.soco.agilent.com/display/ads2009/About+Sinks

memomemomemo wrote on Feb 19^th, 2010, 3:30pm:

What is the circuit mechanism that makes the lock in very low SNR? ( such as minus 30dB)

Generally commercial BERT try to test partial pattern matching during 32bits, 64bits, 128bits, etc. with some judgement for sync or unsync,
so BERT often give message of "Sync_Loss=Unsync" for low Eb/No data.

I don't use commercial BERT with auto synchronization for BER measurement of very low Eb/No data.
Generally such BERT is not useful for burst bit errors or relative long successive bit errors.
The following is my cheap "heppoko" BERT.
http://translate.google.co.jp/translate?u=http%3A%2F%2Fwww.kikusui.co.jp%2Fcatalog%2Fkbm6010_j.html&sl=ja&tl=en&hl=&ie=UTF-8

I use logic analyzer having long memory such as 64Mwords for evaluation of BER by full pattern matching.
http://cp.literature.agilent.com/litweb/pdf/5989-0129EN.pdf
http://cp.literature.agilent.com/litweb/pdf/5989-0024EN.pdf

Title: Re: timing and synchronization
Post by memomemomemo on Mar 2^nd, 2010, 4:04pm

Thanks pancho.

My question was not specific to measurement but related to the design of a system. So the question is:

"How can I synchronize a known low SNR bit sequence i.e with a clean version? (such as correlating a noisy sequence with the same clean high power replica) "

Mehmet

Title: Re: timing and synchronization
Post by pancho_hideboo on Mar 3^rd, 2010, 3:52am

Use "Sliding Correlator".

Simply consider PN generator such as PN9.

memomemomemo wrote on Mar 2^nd, 2010, 4:04pm:

(such as correlating a noisy sequence with the same clean high power replica)

I can't understand what you mean by "high power".
I think it has to be "reference signal having large Eb/No".

It seems that still you can't understand typical "Baseband Communication System Model".

Title: Re: timing and synchronization
Post by love_analog on Apr 20^th, 2010, 8:09am

memomemomemo
Are you looking to build your own setup to measure the BER of a noisy system or just looking for theoretical explanations.

Remember if it is a very noisy signal, you need to remove the noise before you attempt to synchronize, eg filtering etc.