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Modeling >> Semiconductor Devices >> How foundries make low vt mosfet
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Message started by rfmems on Mar 18^th, 2010, 9:23am

Title: How foundries make low vt mosfet
Post by rfmems on Mar 18^th, 2010, 9:23am

In the pcell, low vt transistors have a extra 'lowvt' (or other similar names) layout compared to normal transistors.

What does this layer actually mean during processing in foundries? What do they do to lower the vt?

Title: Re: How foundries make low vt mosfet
Post by Geoffrey_Coram on Mar 18^th, 2010, 10:02am

Don't they change the doping level in the channel?

Title: Re: How foundries make low vt mosfet
Post by rfmems on Mar 19^th, 2010, 1:01am

I am not very sure.
Doesn't native device have even lower vt? and actually there is some step to increase the vt in process?
I couldn't find related literature though.

Title: Re: How foundries make low vt mosfet
Post by vivkr on Mar 19^th, 2010, 3:32am

Hi,

The Vt is adjustable with doping, and that's what is used. Transistors with different Vt are made with different levels of doping as already observed in one reply.

The very same implant which is used for raising the Vt of FETs which would otherwise be formed depletion mode can also raise the Vt by a lower amount if administered in a smaller dose. By the way, I am not sure if one still gets normally ON FETs without an extra implant in the processes used nowadays. However, the principle remains the same.

The standard formula for computing the threshold contains terms related to work function and doping and you can find it in any device physics text. Try Tsividis for instance.

Vivek

Title: Re: How foundries make low vt mosfet
Post by aLittleKnowledge on Jul 13^th, 2010, 4:03am

With small geometry poly-gate processes the gate has the same doping type as the channel. Typically (not always) this results in a depletion device in the absence of threshold adjust.
Even smaller geometries use metal gates, and the metal's work-function is selected to allow the well doping to be optimised for short-channel effects

Title: Re: How foundries make low vt mosfet
Post by Colbhaidh on Nov 30^th, 2010, 6:48am

In modern processes the cmos transistors sit inside doped wells: nmos sits in p-doped well, pmos sits in n-doped well. During the implant process for the well, there may be 2 or 3 implants: for example the nmos p-well would get the deep P-type dopant that forms the well a fairly shallow anti-punch through doping and a shallow surface threshold adjust implant.
The standard threshold implant would give the nominal device.
There may then be options for Low Vt and Low Power transistors. These additional implants either decrease the Vt to give a faster transistor but with higher off state leakage or increase the Vt to give a slower transistor but much lower off state leakage and thus low power.
They always require an additional mask layer that changes the VT for those transistors that are fast or low power. So these options are always more expensive.