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Simulators >> Logic Simulators >> spectreVerilog simulation problem
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Message started by jsun on Apr 3^rd, 2010, 1:13pm

Title: spectreVerilog simulation problem
Post by jsun on Apr 3^rd, 2010, 1:13pm

Hi there,

I am designing ADC. And I have analog part and digital part, so I used spectreVerilog for simulation. Now I met a weird scenario.

I synthesized verilog code by dc and imported it into cadence. Before that, I simulated synthesized verilog code in modelsim and it works properly. However, I put this same code in cadence and run spectreverilog, it only runs for first 10 clk cycles and then all the signals become stable, no more change. It should not be like that. I cannot figure out what's wrong.

Any help?

Thanks...

JSun

Title: Re: spectreVerilog simulation problem
Post by Andrew Beckett on Apr 7^th, 2010, 7:02am

Bear in mind that if using spectreVerilog, you are using VerilogXL, which is a very, very old flavour of Verilog.

Apart from that, it's virtually impossible to help you. Could be anything and with nothing to go on, I'd have to be psychic to be able to know what the problem was!

Andrew.