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Simulators >> AMS Simulators >> ncelab transistion argument
https://designers-guide.org/forum/YaBB.pl?num=1270567529

Message started by Rizzo on Apr 6^th, 2010, 8:25am

Title: ncelab transistion argument
Post by Rizzo on Apr 6^th, 2010, 8:25am

Hello. Iam a student working on my diploma thesis and iam reletivily new to analog modeling.
Iam to use the ams designer to create a model for an energy supply and verify a module of the supply i built in schematics. This i extract with amsdirect to veriog-ams code. 'This is the therory so far. My tests worked out quit well. I worked myself through most of our designframework. like ADE L, nclog ncelab and ncsim. most of my testcircuits are working so far.

Now I need a clock generator. So i used an an example from the designersguide to verilog ams.

Code:

`include "disciplines.vams"

module clock_generator(p,n);
electrical p,n;

parameter real clk_period = 10n from (0:inf), //Periode in Sekunden
clk_ratio = 0.5 from (0:1), //Clock Verhältnis
clk_high = 5.0, //Spannung von HIGH in Volt
clk_low = 0.0 from (-inf:clk_high), //Clock LOW in Volt
trise = 1n from [0:inf), //Trise in Sekunden
tfall = 1n from [0:inf); //Tfall in Sekunden

analog begin
@(timer(0,clk_period))
begin
V(p,n) <+ transition(clk_high,
clk_period*clk_ratio - trise/2,trise);
V(p,n) <+ transition(clk_low,
clk_period - tfall/2,trise,tfall);
end
end
endmodule

my problem ist, that i can compile this with ncvlog -AMS without a problem, but ncelab says, that the transition statement is not allowed in this context ("conditionally-executed statement or in an expression") and that i use a contribution statement and should delete it.

Can someone tell me, why the transition statement isnt allowed and how i can create a clk_gen is verilog-A?

The best way would be to use the spectre sources (as i understand, ncsim uses for the analog part of the simulation spectre) but until now i wanst able to do that. I could not found a detailed guide how to use the simulator sources in a vams netlist.

Title: Re: ncelab transistion argument
Post by Andrew Beckett on Apr 7^th, 2010, 7:38am

The problem is that neither the contribution nor the transition would be evaluated at every timestep - and so they would not be defining the appropriate equations or remembering the transitions from each iteration.

You also have two contribution statements on the same pair of nodes - these will end up as voltage sources in series.

Best thing is to attend a training class on Verilog A or Verilog AMS (Cadence offers these, as I'm sure do others) or read a good book such as http://www.designers-guide.org/Books/#Kundert-2004

Regards,

Andrew.