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Simulators >> Logic Simulators >> Simulating artisan libraries
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Message started by Murat H. Eskiyerli on Apr 8^th, 2010, 8:14am

Title: Simulating artisan libraries
Post by Murat H. Eskiyerli on Apr 8^th, 2010, 8:14am

We got access to Artisan 0.25um logic libraries through Europractice. When I downloaded the library, I was faced a bunch of directories including information for place & route tools, cadence/synopsys symbols and a verilog descriptions in verilog.v.
What I gather, I can only instantiate the library cells as symbols, and maybe simulate them. Now, the question how I can use this verilog.v file to use in simulations. I understand I need to use spectreverilog simulator with hierarchy editor and then use mixed-mode simulation menu to partition the design. Only thing missing is how to tell the simulator where to find the verilog descriptions of symbols.

Any ideas would be much appreciated.

Title: Re: Simulating artisan libraries
Post by Andrew Beckett on Apr 11^th, 2010, 2:48am

Well, spectreVerilog is rather an old mixed-signal simulation interface. You could use AMS Designer instead (ams as the simulator) which is much more modern.

From spectreVerilog, you can go to Simulation->Options->Digital and give the paths to the Verilog files (something like -y or -v on the form). There are similar options for AMS.

If you are only doing digital simulation (i.e. no transistor level), then you could use the direct NC Verilog interface (from the schematic, do Tools (or Launch)->Simulation->NC Verilog (for example)).

Sorry the answer is not that precise - I don't have to tools to hand to be able to answer more precisely.

Regards,

Andrew.

Title: Re: Simulating artisan libraries
Post by bernd on Apr 21^st, 2010, 2:00am

Another way may be to import your verilog library (*.v) as functional view to your symbol library. Then the Hierarchy Editor can use the functional
view for the std. cells.
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