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Design >> High-Speed I/O Design >> Matching Delay Paths
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Message started by jiesteve on Apr 21^st, 2010, 10:37am

Title: Matching Delay Paths
Post by jiesteve on Apr 21^st, 2010, 10:37am

Hi all,

I'm working on matched delay paths for a high speed i/o interface. Because of area constraints we cannot match metal routing lengths. We are looking into the following scheme below:

Could this scheme work? I'm worried about the delays tracking with process variation

Title: Re: Matching Delay Paths
Post by love_analog on Apr 22^nd, 2010, 4:24pm

If I understood your question correctly, this will not work.

Can you perhaps serpentine the short wire to make it match the long wire.

Title: Re: Matching Delay Paths
Post by jiesteve on Apr 22^nd, 2010, 5:38pm

No, we don't have the room available to serpentine the short routes....

This is a hard problem, because the long route is 4000um, the short one is 500um and the delays need to be within +/- 200ps.. Can you think of any other schemes?

Title: Re: Matching Delay Paths
Post by love_analog on Apr 26^th, 2010, 10:41am

Anything else you do will always have this issue that you may be able to nominally match but over skew you may have issues. In addition, the fab might not model that correctly so your silicon will not match sim. Most fabs do not model interconnect skew that well.

Title: Re: Matching Delay Paths
Post by loose-electron on Apr 27^th, 2010, 12:32pm

put in a phase shift interpolation system and do a phase alignment and calibration routine.

Think string of inverters with a mux to pick the delay.

Or, synchronize using phase shifted clock and then re-sync in phase.

Try to adjust metal lines to compensate for variance in transistors will come up to bite you.

Serpetine path balancing is a possible improvement as well, and yes you can fiit it if you want (willing to wager?)

;)