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Simulators >> RF Simulators >> Transistor fmax simulation
https://designers-guide.org/forum/YaBB.pl?num=1272508752

Message started by unevb on Apr 28^th, 2010, 7:39pm

Title: Transistor fmax simulation
Post by unevb on Apr 28^th, 2010, 7:39pm

Is it possible to build a testbench to simulated the fmax of a transistor?

Unlike ft, where we are only dealing with current gain, fmax is the point where the power gain is 0dB. So do we need to design an input matching network to match the input port to the Transistor input impedance every time we resize the transistor? What should be the resistance of the output port?

Regards
Venu

Title: Re: Transistor fmax simulation
Post by pancho_hideboo on Apr 28^th, 2010, 10:56pm

unevb wrote on Apr 28^th, 2010, 7:39pm:

Is it possible to build a testbench to simulated the fmax of a transistor?

Simply do S-parameter analysis.

MAG(Maximum Available Power Gain), MSG(Maximum Stable Power Gain) and U(Mason's Unilateral Power Gain) are calculated from S-parameters.

For example, MAG and MSG are calculated by using the following function in Agilent Post Processing Environment.
http://edocs.soco.agilent.com/display/ads2009/max+gain%28%29

"fmax" is a frequency at 0dB for "MAG" or "U".

I use Agilent ADS with optimizer for this purpose.
All source codes of original prepared functions exist in "$HPEESOF_DIR/expressions/ael".
So we can see definitions of functions easily and create my custom function easily by modifying them which are commonly usable in ADS native, RFDE and GoldenGate.

"Gumx" of Cadence Direct Plot form is "Maximum Unilateral Transduder Gain" not U(Mason's Unilateral Power Gain) .
So I think "Gumx" should be renamed to "GTU_max".

http://www.edaboard.com/viewtopic.php?t=377255

If you will use Cadence Spectre, you should confirm validity of Cadence OCEAN function's definitions.
http://www.designers-guide.org/Forum/YaBB.pl?num=1266403928/11#11

Title: Re: Transistor fmax simulation
Post by unevb on Apr 29^th, 2010, 11:48am

Thanks for the reply!

Just one further doubt. Is the fmax of the transistor a function of the load resistance it is driving? The S21 of the circuit will be a function of R(load). That is what is confusing me.

The analytical expression for fmax shows that it is only a function of device parasitic resistance, capacitance , gm and gds

Title: Re: Transistor fmax simulation
Post by pancho_hideboo on Apr 29^th, 2010, 11:57am

unevb wrote on Apr 29^th, 2010, 11:48am:

Is the fmax of the transistor a function of the load resistance it is driving?

No.

For example, see equation for U by Y-parameter.
Small signal Y-parameter are not dependent on reference impedances.

unevb wrote on Apr 29^th, 2010, 11:48am:

That is what is confusing me.

Read RF theory text book for very beginner.