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https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> CDR modeling for performance prediction and comparison https://designers-guide.org/forum/YaBB.pl?num=1272944729 Message started by KangSub on May 3rd, 2010, 8:45pm |
Title: CDR modeling for performance prediction and comparison Post by KangSub on May 3rd, 2010, 8:45pm Hi, i'm KangSub. I have been studying how to estimate and compare the performance of the CDRs in design step. I read the Kundert's recent paper "Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits", 2009. You can see this paper on the main page. In that paper, To calculate the jitter transfer, the phase domain model is used. As a results, jitter transfer is equivalent to the transfer function of the phase domain model.(page 16, eq(20)) In my opinion, however, the jitter component included in the phase domain model is only random jitter(RJ) component(PD noise and VCO phase noise). So, deterministic jitter(DJ) component seems to be missed. Are there anybody to explain about it? or another opinions? Thanks. |
Title: Re: CDR modeling for performance prediction and comparison Post by Ken Kundert on May 3rd, 2010, 11:10pm The Random Jitter (RJ) and Deterministic Jitter (DJ) are handled separately. DJ is computed in a simple transient analysis. RJ is computed using the phase domain model. The two come together by way of Tslack when computing the Bit Error Rate (BER). -Ken |
Title: Re: CDR modeling for performance prediction and comparison Post by KangSub on May 4th, 2010, 1:27am Thanks for your very quick reply, Mr. Kundert. I have already understood the point that you mentioned above. To calculate BER, we have to evaluate DJ by simulating the voltage domain model(behavioral or TR level circuits) for about 1000 cycle to build the jitter(DJ) histogram of the recovered clock. And we also have to find RJ by simulating the phase domain model that include the random noise(jitter) components of PD and VCO. We can calculate the BER using the standard deviation of RJ, and peak-to-peak value of DJ and 1-UI. It isn't wrong, is it? As you pointed out, RJ and DJ are concerned separately. And, that is the point of my question, too. In phase domain model, only RJ component is included, but not DJ component. In order to calculate the jitter transfer, I think that RJ and DJ have to be also included. Therefore, it seems to be incorrect to use the only phase domain model (that the only RJ component are included in) for evaluate the jitter transfer. That is my question. Thank you very much for your attention. -KangSub |
Title: Re: CDR modeling for performance prediction and comparison Post by Ken Kundert on May 4th, 2010, 11:32am Okay, I think I understand your point now. It is a good question, one that I have not spent enough time thinking about. My assumption was that the DJ is not strongly affected by the sinusoidal jitter applied to the input. By making that assumption I was able to use small-signal analysis. If my assumption is wrong, then we would need to apply sinusoidal jitter of a particular amplitude when performing a jitter transfer tests, and I don't believe the spec for jitter transfer gives an amplitude for the sinusoidal jitter, only its frequency. -Ken |
Title: Re: CDR modeling for performance prediction and comparison Post by KangSub on May 10th, 2010, 3:26am Sorry for my late reply. I can understand your assumption that DJ is not strongly affected by the sinusoidal jitter applied to the input because DJ arises from the system architecture and operation. However, I can not understand your last sentence. Generally, in order to performing a jitter transfer test, do we have to apply sinusoidal jitter of a particular amplitude and frequency and sweep them? I cannot understand that which relationships exist between your assumption and a jitter transfer test and the spec for a jitter transfer. Please, can you explain that more easily? - KangSub |
Title: Re: CDR modeling for performance prediction and comparison Post by Ken Kundert on May 10th, 2010, 9:15am I just took a look at the Telecordia spec and found the following: Quote:
This suggests that jitter transfer is not a simple linear transfer function as I assumed, which implies predicting jitter transfer using simulation would involve running a series of transient simulations where a sinusoidal jitter is applied to the input to the CDR over a range of frequencies and with an input amplitude equal to 0.1 to 1.0 of the jitter tolerance mask to determine the DJ, and then following that with corresponding phase domain model simulations to determine the RJ, and finally combining those to find the jitter transfer. I have never done these measurements so I have no idea how much the DJ changes as you change the input amplitude of the input jitter. Do you have any experience with this? Is this a significant effect? -Ken |
Title: Re: CDR modeling for performance prediction and comparison Post by love_analog on Jul 29th, 2010, 7:36am I always thought DJ was more of a power supply thing. Because of that we typ simulate the DJ with power supply noise on the PLL/CDR supply. Don't do any frequency shaping analysis on it like we do for RJ. Never had to. |
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