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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Need Verilog A model for Fully differential OTA https://designers-guide.org/forum/YaBB.pl?num=1274783126 Message started by siegi on May 25th, 2010, 3:25am |
Title: Need Verilog A model for Fully differential OTA Post by siegi on May 25th, 2010, 3:25am Could someone please share FD OTA verilog A source code !! Thanks in advance |
Title: Re: Need Verilog A model for Fully differential OTA Post by Geoffrey_Coram on May 25th, 2010, 6:09am What if you take this model: http://www.designers-guide.org/VerilogAMS/basic-models/ideal-opamp/ideal-opamp.va and change it from a V to an I output? I(out): V(in) == 0; |
Title: Re: Need Verilog A model for Fully differential OTA Post by siegi on May 26th, 2010, 4:03am Thank you...but i'm looking for OTA with gain,bandwidth,slew rate, CMRR, PSRR, Power Supply. |
Title: Re: Need Verilog A model for Fully differential OTA Post by Geoffrey_Coram on May 26th, 2010, 4:43am There's another guy on this forum who has a list of points for newbies, including one about how not to expect us to do all your work for you. Have you even tried to write your model? |
Title: Re: Need Verilog A model for Fully differential OTA Post by carlgrace on Jun 25th, 2010, 4:32pm There is a fully-differential opamp model in the bmslib, but I have had some convergence issues using it. I think Geoffrey's suggestion was great. Take an opamp model that has what you want, figure out how it works, and then modify it to be fully differential. Don't be afraid of it, it isn't all that hard. You just have to add an extra output, invert it with respect to the original output and make sure they are both referred to the same common-mode voltage. Good luck! |
Title: Re: Need Verilog A model for Fully differential OTA Post by eelxpeng on Mar 6th, 2014, 6:21am I did one with gm, Gain, Output DC Voltage but without slew rate or voltage limit. 'include "constants.vams" 'include "disciplines.vams" module diff_OTA(vip,vin,vop,von,vss) output vop,von; input vip,vin,vss; electrical vip,vin,vop,von,vss; parameter real vcm=1.65, Av=1800, gm=1.8m; real Gout,vodif; analog begin @(initial_step) begin Gout=gm/Av; end vodif=Av*V(vip,vin); I(vop,vss) <+ (V(vop,vss)-(vcm+vodif/2))*Gout; I(von,vss) <+ (V(von,vss)-(vcm-vodif/2))*Gout; end endmodule |
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