The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> VHDL-AMS >> Converting a VHDL code to VHDL-AMS for simulation in Analog Design Environment.
https://designers-guide.org/forum/YaBB.pl?num=1275342392

Message started by pkd on May 31^st, 2010, 2:46pm

Title: Converting a VHDL code to VHDL-AMS for simulation in Analog Design Environment.
Post by pkd on May 31^st, 2010, 2:46pm

Hi all,
I have a VHDL code which I have simulated in modelsim and also synthesized in Xilinx board. But Now I need to put that entire code (The top one has 3 sub-modules in VHDL) into analog design environment to test out the characteristics of the overall system with the other analog blocks.
This is the first time I am trying to simulate an HDL code in ADE, so have very little idea about the flow. So, I would appreciate a bit of hints on how should I go about it in terms of various tools flow. I am having IUS82 tool. I have read the Verilog AMS guide in this comunity and successfully simulated the components like Flip-flops, AND gates ADC etc, but I didn't find any example there where a chunk of VHDL code of considerable magnitude being compiled in VerilogAMS and incorporated in ADE.
I have attached the code for one of my modules as a sample.
Waiting desperately for some useful hints/insights/suggestions/guidance. :)

Title: Re: Converting a VHDL code to VHDL-AMS for simulation in Analog Design Environment.
Post by Marq Kole on Jul 5^th, 2010, 7:58am

If you want to work the analog way: Import the VHDL code into your environment using File -> Import -> VHDL from the CIW. That will give you a library with the VHDL block. You can then instantiate the VHDL block in your schematic. If you have selected the proper connect rules (similar to Verilog-AMS or Verilog examples) you can run your simulation from either ADE or the Hierarchy Editor using the AMS plugin.

Marq

Title: Re: Converting a VHDL code to VHDL-AMS for simulation in Analog Design Environment.
Post by jerome_ams on Oct 26^th, 2010, 8:14am

Basically, there is no need to "convert" your VHDL code. As VHDL-AMS is a superset of VHDL, an VHDL-AMS simulator will simulate VHDL.

Just import your code (i.e. compile it) in the Cadence database.

Cheers,
Jerome