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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Modeling of Divider with Delta-Sigma Modulator in Phase-Domain https://designers-guide.org/forum/YaBB.pl?num=1275390599 Message started by ussmueller on Jun 1^{st}, 2010, 4:09am |
Title: Modeling of Divider with Delta-Sigma Modulator in Phase-Domain Post by ussmueller on Jun 1^{st}, 2010, 4:09am Dear all, I'm currently trying to implement a Delta-Sigma (DS) modulator phase domain model. I have not understood the model in Ken's paper (Predicting the phase-noise and jitter of of PLL based frequency synthesizers, page 24). parameter real n = 0 from [0:inf); // white output phase noise (rads2/Hz) parameter real bw = 1 from (0:inf); // ΔΣ modulator bandwidth parameter real fmax = 10∗bw from (bw:inf); // maximum frequency of concern ... Theta(out) <+ Theta(in) / (ratio + noise_table([ 0, n, bw, n,fmax, n∗pow((fmax/bw),order) ], “dsn”)); The divide ratio consists of the "wanted" part ratio and the delta-sigma noise. Ratio can be a fractional number. The delta sigma noise is modeled with the noise_table function. The noise of the divider is not modeled. Are these assumptions corrrect? What do the parameters n, bw and fmax describe? Is fmax = fref/2? What is meant by DS bandwidth. To my understanding a DS has a constant slope of order*20dB/dec and has no high pass function. How to extract the parameter n? Is it possible to use a transfer function in the z-domain (e.g. (1 - z^-1)^3 for a MASH-111) instead of the noise_table function? Thanks for your support. Thomas |
Title: Re: Modeling of Divider with Delta-Sigma Modulator in Phase-Domain Post by cheap_salary on Feb 10^{th}, 2016, 9:50pm ussmueller wrote on Jun 1^{st}, 2010, 4:09am:
zi_nd() could not work in small signal analysis of Cadence Spectre Verilog-A over very long time. Now zi_nd() can work in small signal analyses such as ac and noise of Cadence Spectre. I confirmed it in Cadence Spectre-14.1. See http://www.designers-guide.org/Forum/YaBB.pl?num=1444923186/6#6 However zi_np(), zi_zd() and zi_zp() still can not work in Cadence Spectre Verilog-A. On the other hand, all of zi_nd(), zi_np(), zi_zd() and zi_zp() can work on Synopsys Hspice Verilog-A even if its version is fairly old. |
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