The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> High-Speed I/O Design >> Digital loop filter for bang-bang type PFD for PLL or PD for CDR https://designers-guide.org/forum/YaBB.pl?num=1279762809 Message started by KangSub on Jul 21st, 2010, 6:40pm

 Title: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by KangSub on Jul 21st, 2010, 6:40pm HI, I'm KangSubI've been studying the design of PLL and CDR.I want to know how to implement the digital loop filter in PLL or CDR.Generally, charge-pump PLL is widely used. In CPPLL, charge pump and loop filter(R1+C1,C2) are used. I want to replace this analog loop filter as digital loop filter. but I don't know how to do that. In CDR, I want to do same replacement.http://home.netcom.com/~chip.f/plls.htmThis is short article about digital loop filter and I found this type of digital loop filter in paper(Yehui Sun, "Analysis of Digital Bang-Bang Clock and Data Recovery for Multi-Gigabit/s Serial Transceivers", CICC, 2009) But, I don't know how to connect the UP/DN signal to the this type of digital loop filter.And, I studied the basic of z-transfrom and can understand the transfer function and can draw the frequency response by hand or using Matlab.  But, when I draw the frequency response of that type of loop filter(Ki = Kp = 1), it was not the frequency response of the low pass filter. It may be because of the wrong value of Ki and Kp. How to decide the Ki and Kp?The following is the Matlab code.z = tf('z',0.1);kp=1;ki=1;hz = kp + ki/(1-z^(-1));ltiviewIn summary,1. How to implement the loop filter of PLL or CDR in a digital manner?2. How to connect the UP/DN signal of PFD or PD to the digital loop filter?3. How to decide the Ki and Kp of the loop filter above?4. Can you recommend me the papers, books, or articles about that?Thank you.-KangSub

 Title: Re: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by raja.cedt on Jul 21st, 2010, 9:34pm hi KangSubi know about design of digital loop filter for pll only..there first you design analog pll parameters like r1,c1,Icp,Kvco and then map those value into digital filter equations...for further reading please refere this. http://web.engr.oregonstate.edu/~hanumolu/PAPERS/cas2_mar_07_dpll.pdfThanks.

 Title: Re: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by KangSub on Jul 22nd, 2010, 8:38am Thanks for your help, raja.cedtAfter reading the paper, I'll comment about that.

 Title: Re: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by raja.cedt on Jul 22nd, 2010, 10:39am hi,  ok..please go through that pap and discuss more. By the way even i want to learn CDR basic design can you please direct me any basic book or pap which can give decent starting .Thanks.

 Title: Re: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by KangSub on Jul 23rd, 2010, 7:37am hi,If you wan to learn the basic of CDR, you can refer to the book of Razavi, "Design of Integrated Circuits for Optical Communications, McGrawHill", and following papers,http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.141.6264&rep=rep1&type=pdforC.K. Yang and M.A. Horowitz, “A 0.8-um CMOS 2.5Gb/s Oversampling Receiver and Transmitter for Serial Links,” IEEE JSSC, vol. 31, pp. 2015-2023, Dec. 1996

 Title: Re: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by KangSub on Jul 23rd, 2010, 7:02pm Hi, raja.cedtI read the Kratyuk's paper. That paper was simple so I could understand well.But, I have several questions yet.First, why the coefficient alpha and beta was approximated to the power of 2?Second, How to implement that type of digital filter? it contains the multiplier. Is there the simple method to implement the multiplier?thanks- KangSub

 Title: Re: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by raja.cedt on Jul 23rd, 2010, 11:21pm hi KangSub,i guess if you use alpha and beta as power of two you could use shift left and shift right operations for multiplication rather than putting a big multiplier. I didn't understand 2nd question like how to implement (use can use direct shift register for Kp implementation and one flop and Ki for another branch)

 Title: Re: Digital loop filter for bang-bang type PFD for PLL or PD for CDR Post by KangSub on Jul 24th, 2010, 1:06am hi, raja.cedti think your opinion is right.2's power of Ki and Kp seems to be selected for implementing the multiplier as simple shift register.thanks for your answer.- KangSub