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Design Languages >> VHDL-AMS >> type check error, problem with terminal
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Message started by chippendale on Jul 23^rd, 2010, 5:57am

Title: type check error, problem with terminal
Post by chippendale on Jul 23^rd, 2010, 5:57am

Hi there,

I have an terminal bus.
terminal test:electrical_vector(0 to3);

I assign a constant through quantity to these terminals.
test(0 to 3) == -10.0e-6;

The output message of the compiler is
"type check error: expression is not a type IEEE.ELCTRICAL_SYSTEM.__THROUGH_ELECTRICAL_VECTOR"
and references to the above given text passage

Any ideas?!

Title: Re: type check error, problem with terminal
Post by chippendale on Jul 23^rd, 2010, 6:59am

Hi,
I found the solution. The assignment has to look like this
test(0 to 3) == (others => -10.0e-6);