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Measurements >> Phase Noise and Jitter Measurements >> The effect of the noise shaping of the loop
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Message started by casual on Aug 2^nd, 2010, 6:30am

Title: The effect of the noise shaping of the loop
Post by casual on Aug 2^nd, 2010, 6:30am

The effect of the noise shaping of the loop can be observed in this spectrum (refer to the diagram)

What does the "noise shaping of the loop" refer to? Does it refer to region #2 in the diagram?

I know that the clk freq can be shaped by loop filter shape in the PLL.

Could we tell the loop BW from this noise shaping effect?

Title: Re: The effect of the noise shaping of the loop
Post by ACWWong on Aug 2^nd, 2010, 2:49pm

Indeed the "noise shaping of the loop" could mean the the loop filter shape, but this terminology can also be used to refer to other things in the PLL (depending on the circumstances/architecture of the PLL....)

Anyway in your case its the loop BW is about 10MHz (roughly the width of the plateau at 2). The hump at 2 and roll-off between 2 and 3 is due to the net loop filter response. Levelling-off at 3 could be due to wideband noise of PLL signal (e.g. due to buffers etc.), but also analyser noise floor.

hope this helps... for more information on PLL loop dynamics, Dean Banerjee from National semiconductor writes good application notes. Google him!

cheers

aw

Title: Re: The effect of the noise shaping of the loop
Post by casual on Aug 2^nd, 2010, 8:58pm

thx for your reply to confirm my understanding.

Since the loop BW can be observed from the spectrum, we could also see the overshoot response. The little hump there indicates the overshoot.
am I right?

Title: Re: The effect of the noise shaping of the loop
Post by Mayank on Aug 3^rd, 2010, 4:47am

Quote:

Since the loop BW can be observed from the spectrum, we could also see the overshoot response. The little hump there indicates the overshoot.
am I right?

Wrong.

Judging PLL XF from PLL Phase noise plot could be tricky.
The peaking that you see in phase noise plot in region 2 could be from either osc. phase noise dominating due to low BW, or i/p jitter peaking due to peaking in XF or BOTH.

Hence, to obtain loop response params, simulate loop characterstics for PLL XF separately, instead of judging them from PLL phase noise plot.

--
Mayank.

Title: Re: The effect of the noise shaping of the loop
Post by casual on Aug 3^rd, 2010, 5:22am

I am aware that it is tricky.

But it helps in the silicon debug or measurement to give rough idea on the PLL BW & response.

I could extract the close loop response from transient analysis.
BTW, I still do not know how to obtain PLL transfer function. Do you know?

Title: Re: The effect of the noise shaping of the loop
Post by love_analog on Aug 7^th, 2010, 1:23pm

you cannot easily obtain PLL Xfunction from the spectrum analyzer. What you can do is compare your measurement with sims and vary the sim parameters to make it match measuremnts. This will at least give you an idea of what could be off in your sims.

Title: Re: The effect of the noise shaping of the loop
Post by SSA@A on Jun 13^th, 2011, 9:22pm

FYI.
Though this is not the answer for your question....

General topics on PLL design and measurement is discussing on this application note.
"Boosting PLL Design Efficiency From free-running VCO characterizations to closed-loop PLL evaluations"
http://cp.literature.agilent.com/litweb/pdf/5989-9848EN.pdf

here's a solution for your PLL design.
http://www.agilent.com/find/ssa