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Modeling >> Semiconductor Devices >> capacitance in device models
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Message started by c1000 on Aug 4^th, 2010, 1:29pm

Title: capacitance in device models
Post by c1000 on Aug 4^th, 2010, 1:29pm

In physics-based device models, like BSIM models, the parasitic capacitance is evaluated by the derivative of charge with respect to corresponding terminal voltage.
If the device is modeled as a current source and 16 or less capacitors, why not using capacitance directly but calculating charge for caps?
does charge must be evaluated for circuit simulation?

Title: Re: capacitance in device models
Post by Geoffrey_Coram on Aug 5^th, 2010, 6:48am

c1000 wrote on Aug 4^th, 2010, 1:29pm:

does charge must be evaluated for circuit simulation?

Yes.

Ken's book (Designer's Guide to Spice & Spectre) shows why -- charge conservation. BSIM3/4 model the device as currents and charges -- four, one for each terminal. I suppose you could count it differently: channel charge (split into four components), plus junction and overlap caps (which are two-terminal capacitors).

Not sure what you meant by "parasitic capacitance" -- the channel charge is not parasitic.