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Simulators >> AMS Simulators >> A problem encountered in AMS simulation
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Message started by chip on Sep 6^th, 2010, 1:59am

Title: A problem encountered in AMS simulation
Post by chip on Sep 6^th, 2010, 1:59am

I simulate my analog circuit with verilog code for digital using AMS simulator in ADE, it displays the error message when elaborating as following:
Digital or mixed-bus connections(with digital) not supported at Spice boundry.
I can not find any useful information about that on the internet,Does anyone know the reason? Thanks a alot. :-?

Title: Re: A problem encountered in AMS simulation
Post by ywguo on Sep 13^th, 2010, 8:17am

Hi,
Did you setup any connect rule? What's the analog simulator?

Yawei

Title: Re: A problem encountered in AMS simulation
Post by AMS_ei on Apr 19^th, 2017, 10:08am

Hi,

I am looking at this post now. I am not sure if this problem has been resolved from your end. However, I have a suggestion for you.

Create an amsd block in an .scs file ( say amscf.scs) and there use portmap subckt=<subckt_name> porttype=name as shown below:

amsd {

portmap subckt=<subckt_name> porttype=name
config cell=<cell_name_generally_module_name> use=spice

}

This will generate a portbind file which will have all the spice and verilog port mapping.

Hope this helps.

Thank you.