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Design >> High-Speed I/O Design >> 128b/130b encoding in PCI-Express Gen3
https://designers-guide.org/forum/YaBB.pl?num=1284927313

Message started by neoflash on Sep 19^th, 2010, 1:15pm

Title: 128b/130b encoding in PCI-Express Gen3
Post by neoflash on Sep 19^th, 2010, 1:15pm

The change in encoding schemes also includes a scrambling/descrambling algorithm as follows:

x23 + x21 + x16 + x8 + x5 + x2 + 1.

It is quite interesting that this scrambling scheme only use x23 as the most significant bit, while introduced 6 feedback nodes. Compared with x59+x38+1 in 64b/66b scrambler, it is very different.

My question is that whether that many (6) feedback nodes will worsen the error propagate? (each error bit has 6 chances to ruin other bits.)

Welcome to join this discussion.

Title: Re: 128b/130b encoding in PCI-Express Gen3
Post by loose-electron on Sep 24^th, 2010, 3:05pm

Haven't studied it, but you are going to need the whole story, coding structures, bandwidth, ECC methods, etc.

Coding theory and ECC is a field of math/engineering that can get a bit "too interesting" for some. I went that path for a while in the field of disk drives, the coding and ECC things there are pretty complex.

What you mention of the capability to "mess up" 6 other bits does not take into account the detection scheme and the weighting of each delay tap. I expect whats getting used is a Viterbi detector and some for of "partial response" with "maximum likelihood" detection...The contribution from a single bit is actually spread across several time windows and has to be properly weighted in (or out) of the adjacent windows.

Anyhow it becomes a communication channel problem with needs to look at the model end to end, Some things will be in the PHY levels but a lot is not.

Title: Re: 128b/130b encoding in PCI-Express Gen3
Post by neoflash on Sep 13^th, 2011, 4:47pm

I see. Thanks.