The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Semiconductor Devices >> Re: Snapback in LDMOS
https://designers-guide.org/forum/YaBB.pl?num=1286793906

Message started by ujwal on Oct 11^th, 2010, 3:45am

Title: Re: Snapback in LDMOS
Post by ujwal on Oct 11^th, 2010, 3:45am

Hi,

I am trying to write a compact model for snapback effect in LDMOS. KCL and KVL for the Equivalent circuit results in a node voltage of the form :
V(n,0) = C1+ C2*exp(V(n,0)/Vt) ; (C1>>C2)

This has two solutions for V(n,0) . What do i have to do to get the higher value solution? My code in VerilogA always gives me the lower value solution for V(n,0 ) which is close to trivial solution.

Thanks,

Ujwal