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Modeling >> Semiconductor Devices >> How are PDK's made?
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Message started by somisetty on Nov 21^st, 2010, 8:08pm

Title: How are PDK's made?
Post by somisetty on Nov 21^st, 2010, 8:08pm

Hi all,

any one tell me "how are PDK's made,for Transistors?i meant to ask how are mos device models made,which are used for circuit simulations?

Thanks

Title: Re: How are PDK's made?
Post by raja.cedt on Nov 22^nd, 2010, 3:22am

what do you mean by models? for process foundry will characterize all bsim modeled parameters correspoding to every element.

Thanks.

Title: Re: How are PDK's made?
Post by anil reddy on Nov 22^nd, 2010, 7:57am

hi,

its a complex process in which all the intrinsic parameters of the MOS device are measured and based on that data a model of the device will be formed which replicates the device behaviour in simulations. it is usally done by a foundry on some test structures.

a PDK consists of all the component models which are available in that process. for example high Vt, low Vt transistors, inductors ..etc.

thank you..

Title: Re: How are PDK's made?
Post by Colbhaidh on Nov 30^th, 2010, 6:18am

During the R&D stage of a new process node, there will be several design of experiments around each component that will be available to the designers in the new technology. For a mos transistor, these will include variations in gate oxide thickness, channel implants, drawn sizings, spacings between junctions etc, etc.
Once the desired response surface for the transistor is agreed upon, then transistors can be made with nominal target values for all process parameters and all device specification parameters (slow, fast etc).
These are used for parameter extraction of the spice models which can mean extracting hundreds of BSIM4.X parameters for each transistor at a range of temperatures and and extremes of expected processing (3 sigma for example). The spice model is then fixed for this component and used for the PDK. The symbol for the component is also designed (for example a LDMOS device may have six or more nodes, not just gate drain source and body). The P-Cell layout is also designed and the parasitics as a function nof the layout are derived. All these go together into the PDK.
So a designer may just see a simple graphic of an nmos transistor that can be moved about the ciomputer screen with a wee mouse. But behind that simple symbol for a nmos transistor was years of man hours.

Title: Re: How are PDK's made?
Post by haykp on Dec 1^st, 2010, 12:34am

Please refer to ciranova docs for more info:http:
//www.ciranova.com/products/