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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Problem about assura QRC and post-simulation with ibm cmrf8sf
https://designers-guide.org/forum/YaBB.pl?num=1290650618

Message started by akon on Nov 24^th, 2010, 6:03pm

Title: Problem about assura QRC and post-simulation with ibm cmrf8sf
Post by akon on Nov 24^th, 2010, 6:03pm

Hi,
I'm using IBM cmrf8sf with ic614 & assura410 & EXT914. and there is problem when I run QRC and do post-simulation of a simple inverter, the netlist below is extracted from the av_extracted view which I get from QRC. I think the net07 and \1\:net07 should be connected by a parasitic resistor or directly connected, or that definitely would make the circuit not working, I'm sure that it's not netlisting problem because I can see the non-connection in the av_extracted view. The problem would be gone if I add a pin on the location of the net07, and that really confuses me, did anyone meet this problem? Thanks in advance!

// Library name: akon_test
// Cell name: DIG_cell_inv_qrc
// View name: av_extracted
subckt DIG_cell_inv_qrc_av_extracted A vddd vntie vptie vssd
avD1189_1 (vntie \1\:vptie) diodenwx area=8.155e-12 perim=1.264e-05 \
t3well=0 dtemp=0.0
rj4 (\3\:A A) resistor r=4.6959 c=0
rj11 (\1\:vddd vddd) resistor r=2.4794 c=0
rj1 (\1\:vptie vptie) resistor r=4.5261 c=0
rk_1_2 (\2\:A \3\:A) resistor r=7.1907 c=0
rk_1_1 (\1\:A \2\:A) resistor r=25.683 c=0
T1 (\1\:net07 \1\:A \1\:vddd \1\:vptie) lvtpfet l=1.2e-07 w=3.2e-06 \
nf=1 m=1 par=1 ngcon=1 ad=1.76p as=1.76p pd=7.5u ps=7.5u \
nrd=0.0697306 nrs=0.0697306 rf_rsub=1 plnest=-1 plorient=-1 \
pld200=-1 pwd100=-1 lstis=1 lnws=1 rgatemod=1 rbodymod=0 panw1=0p \
panw2=1.2e-14 panw3=1.2e-14 panw4=1.2e-14 panw5=1.2e-14 \
panw6=2.4e-14 panw7=4.8e-14 panw8=4.32e-13 panw9=9.6e-14 \
panw10=1.2e-13 sa=5.5e-07 sb=5.5e-07 sd=0 dtemp=0
T0 (net07 A vssd vntie) lvtnfet l=1.2e-07 w=1e-06 nf=1 m=1 par=1 \
ngcon=1 ad=0.55p as=0.55p pd=3.1u ps=3.1u nrd=0.230366 \
nrs=0.230366 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
lstis=1 lnws=1 rgatemod=1 rbodymod=0 panw1=0p panw2=0p panw3=0p \
panw4=0p panw5=0p panw6=0p panw7=1.2e-15 panw8=2.4e-14 \
panw9=4.8e-14 panw10=4.68e-14 sa=5.5e-07 sb=5.5e-07 sd=0 dtemp=0
ends DIG_cell_inv_qrc_av_extracted
// End of subcircuit definition.