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Design Languages >> VHDL-AMS >> Warning messages related to latches
https://designers-guide.org/forum/YaBB.pl?num=1291283208

Message started by PabloSistemas on Dec 2^nd, 2010, 1:46am

Title: Warning messages related to latches
Post by PabloSistemas on Dec 2^nd, 2010, 1:46am

Hi there,

I've developed a code for a register which takes the values present at its two inputs named "input_1" and "input_2" when the value of the input "flanco_subida" is '1' and shows at the output the values taken from these two inputs until a new '1' appears at "flanco_subida".

The code I've written is shown below

Code:

LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY SampleHolder IS
PORT (input_2, flanco_bajada, clk, reset: IN std_logic;
input_1: IN std_logic_vector(3 downto 0);
output_1: OUT std_logic_vector(3 downto 0);
output_2: OUT std_logic
);
END SampleHolder;

ARCHITECTURE SampleHolderArch OF SampleHolder IS
--Declaracion de estados
TYPE Estado IS (EInicio, EDetectado, EMantenerSalida);

--Señales auxiliares para la codificacion del estado actual y el estado siguiente
SIGNAL tEstadoActual, tEstadoSiguiente: Estado;
SIGNAL aux_1: std_logic_vector(3 downto 0);

BEGIN
--Proceso dedicado a la logica de estado
LOGICA_ESTADO: PROCESS (tEstadoActual, flanco_bajada)
BEGIN
CASE (tEstadoActual) IS
WHEN EInicio =>
IF (flanco_bajada = '1') THEN
tEstadoSiguiente <= EDetectado;
ELSE
tEstadoSiguiente <= EInicio;
END IF;
WHEN EDetectado =>
tEstadoSiguiente <= EMantenerSalida;
WHEN EMantenerSalida =>
IF (flanco_bajada = '1') THEN
tEstadoSiguiente <= EDetectado;
ELSE
tEstadoSiguiente <= EMantenerSalida;
END IF;
END CASE;
END PROCESS LOGICA_ESTADO;

--Proceso dedicado a la memoria de estado
MEM_ESTADO: PROCESS (clk, reset)
BEGIN
IF (clk'EVENT and clk = '1') THEN
IF (reset = '1') THEN
tEstadoActual <= EInicio;
ELSE
tEstadoActual <= tEstadoSiguiente;
END IF;
END IF;
END PROCESS MEM_ESTADO;

--Proceso dedicado a la logica de salida
output_1 <= input_1 WHEN tEstadoActual = EDetectado ELSE "0000";
--"0000" WHEN tEstadoActual = EInicio;
output_2 <= input_2 WHEN tEstadoActual = EDetectado ELSE
'0' WHEN tEstadoActual = EInicio;

END SampleHolderArch;

The problem that I have is that, when I compile my code with Quartus II, I get a message saying "Warning: Timing Analysis is analyzing one or more combinational loops as latches" / "Warning: Node "SampleHolder|output2|combout" is a latch".

If I change the line

output_2 <= input_2 WHEN tEstadoActual = EDetectado ELSE
'0' WHEN tEstadoActual = EInicio;

for

output_2 <= input_2 WHEN tEstadoActual = EDetectado ELSE
'0';

the warning message disappears, but, as expected, the behaviour of the system is not as desired.

Help from anyone?

Thanks so much