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Measurements >> Other Measurements >> measurement of a 22 bit delta-sigma-adc
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Message started by DDC on Dec 21^st, 2010, 3:50am

Title: measurement of a 22 bit delta-sigma-adc
Post by DDC on Dec 21^st, 2010, 3:50am

hallo,

I try to design a offchip measurement setup to evaluate nonlinearities of a 22 bit adc. I simulated histrogram tests using sinus waves and ramps. I have noticed that such high resolution ramp waveform generators are not available and by using a sine wave the test time would be more than two days to get enough samples for inl/dnl calculation. Then I found an IEEE paper about testing high resolution adc's http://ieeexplore.ieee.org/search/freesearchresult.jsp?newsearch=true&queryText=Testing+of+High+Resolution+ADCs+Using+Lower+Resolution+DACs+via+Iterative+Transfer+Function+Estimation&x=39&y=12. I built a model of this testsetup und matlab but there are some problems with solving the equation system. Does somebody have another idea how can I test such a high resolution adc ? I haven't got any idea. Thanks for the answers.

Title: Re: measurement of a 22 bit delta-sigma-adc
Post by widlar on Dec 31^st, 2013, 10:04am

Well, I have kind of the same problem.

I've made a 21-bit ADC. However the output rate is 25Hz. So, it takes ages to measure DNL especially if you want to hit each code several times for a histogram.

For the case of INL, you don't need to hit every code. Just take a number of samples over the full range, and you'll immediately see the deviation from an ideal transfer characteristic. But, be aware that there's no such 22-bit linear signal generator. So, you need to measure your input signal with a high linearity ADC or digital multimeter. I use Keithley 2002 to measure my DAC's output. With enough averaging, it has less than 1-ppm linearity. So, you can take the difference between your ADC's output and input and get the INL data.

For DNL, I'm still not sure how to measure it considering the time needed. Drift wouldn't effect the differences between each code I guess, but it would be meaningless to integrate that DNL data to get INL from DNL. So, that's a really tough problem.

BTW: I'm now working on a 20-bit ADC for audio bandwidth. Is there anyone who has any idea how to generate high linearity sine wave for such resoultion? SNR is not a big deal as far as I see but the most critical spec of the ADC would be THD, o I want a really pure sine. I think I need to just specify some frequencies and make a very narrow bandpass filters. But it would be really hard to make it in very low frequencies I guess. I've found NI PCI-4461 card which has perfect analog input charachteristics but it's DACs lacks of the THD performance I need.

Title: Re: measurement of a 22 bit delta-sigma-adc
Post by rf-design on Apr 19^th, 2014, 5:14am

One of the best combining approaches for the state-variable-oscillator:

http://www.sg-acoustics.ch/analogue_audio/publications/pdf/low_distortion_oscillator_design.pdf

Most state-varaible-oscillators designs using 1-4 phase rectifier circuits which need ripple filtering. But exact this filtering slows down the state-variable amplitude control. In effect the increase/decrease of the amplitude because of the pole position shift around the imaginary axis is faster than the control. So in effect secondary amplitude limiting effects in the RC-Amp-Loop determine the amplitude. The amplitude regulation loop have only an slow adjusting effect. For the regulation operation it mean that supply and noise-pick up effects are more critical.

There are two candidates for amplitude regulation w/o filtering delay.

ampl=vp*cos^2(omega*t)+vp*sin^2(omega*t)

and

zero crossing directed sampling of of I and Q state

Both generate ripple depending on implementation accuracy but could provide low close carrier amplitude regulation noise.

Furtheron the author above choose a dedicated opamp and use a amplitude control which provide more linearity in relation to control range.

The result seem to be better than -140dB and good for 22bit ADC verification.