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Simulators >> Logic Simulators >> Generating liberty (.lib) files for analog blocks.
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Message started by BillH on Dec 21^st, 2010, 11:04am

Title: Generating liberty (.lib) files for analog blocks.
Post by BillH on Dec 21^st, 2010, 11:04am

What is the best way to generate liberty (.lib) format timing files for an analog block (e.g. PLL) to be used in a digital top level integration flow?

So far, we have basically used a combination of legacy liberty files and hand-editting new information.

But I was wondering if there are standard tools or flows used for this step?

Thanks.

Title: Re: Generating liberty (.lib) files for analog blocks.
Post by haykp on Dec 23^rd, 2010, 12:12am

You can use synopsys libertyNCX tool to generate the lib file.
The tool mainly needs extracted input, model files and hspice simulator access.

Title: Re: Generating liberty (.lib) files for analog blocks.
Post by Andrew Beckett on Jan 2^nd, 2011, 12:38pm

There is also a capability in DCM (part of ADE GXL) in Cadence's IC61 release which can help with generation of .lib for mixed signal blocks.

Best Regards,

Andrew.