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Analog Verification >> Analog Functional Verification >> analog circuits synthesis tools
https://designers-guide.org/forum/YaBB.pl?num=1294177745

Message started by koma on Jan 4^th, 2011, 1:49pm

Title: analog circuits synthesis tools
Post by koma on Jan 4^th, 2011, 1:49pm

dear all,

I am new to the tools used for analog circuit design so I have some questions regarding the capabilities of the tools and the best tools to use.
in digital design I used to write an RTL code in verilog, synthesize it to generate a a gate level netlist file...i just wanna ask if we have the same procedure in analog circuits design..I started looking for verilog AMS which allows me to write the behavioral model for a certain analog block but am worried if i can take this code to generate a transistor level circuit with certain transistor sizes or synthesize it and do place and route .
I have access to cadence tools that i am using to write my verilog ams code.

regards,

Title: Re: analog circuits synthesis tools
Post by Andrew Beckett on Jan 5^th, 2011, 5:30am

See http://www.designers-guide.org/Forum/YaBB.pl?num=1165836451/2#2.

Whilst various synthesis tools have been created for specific classes of circuits, there aren't really any good general solutions. Years ago I wrote (along with some colleagues) a switch capacitor filter synthesis tool, which worked pretty well - but it was targeted at one specific type of circuit.

So normally it needs a designer to "synthesize" the design from a high level spec (or model) to transistor level (of course, you may be able to build the design from existing blocks such as opamps, data converters, comparators, etc).

The closest approach that has been reasonably successful is using optimization to size the design once the topology has been developed. This is mainly beneficial in terms of design centering and yield improvement though (and relies on you capturing the appropriate measurements and specifications to ensure that the optimizer is sufficiently well constrained).

Regards,

Andrew.

Title: Re: analog circuits synthesis tools
Post by koma on Jan 5^th, 2011, 11:19am

thanks for the reply,
it seems i am missed with the procedure that I should follow...for example I have an ADC module written in verilog AMS what are the next steps I should follow to end up with a schematic or transistor level netlist...I know it is a simple question but can you advise me regarding that.
regards,

Title: Re: analog circuits synthesis tools
Post by Andrew Beckett on Jan 5^th, 2011, 1:19pm

You need to hand craft the design. There's no push button to convert from a behavioural model to a transistor level design.

You should read some books on Analog Design to get a good idea of the process.

Best Regards,

Andrew.

Title: Re: analog circuits synthesis tools
Post by koma on Jan 5^th, 2011, 1:42pm

actually am familiar with the hand calculation and transistor level design procedure for basic analog components like opamp..but I thought there is an easier way that I can follow to design a larger analog blocks by just providing the functionality.

but can I understand from your last post that there is no equivalent procedure that can be followed in analog similar to the digital one(RTL(behavioral model)-->synthesis-->gate level(structural model))

regards,

Title: Re: analog circuits synthesis tools
Post by loose-electron on Jan 30^th, 2011, 5:46pm

Many attempts have been made to do automated analog design. Except for extremely limited cases of specific circuits, all have failed.

Going from RTL Verilog to a digital synchronous chip has largely been automated.

Not the case for analog design. If you have not done analog design it is time to go back to school in this area to become familiar with the issues involved.

Doing a Verilog AMS model of a converter is fairly straightforward, but gettting the design functional at the transistor level is orders of magnitude more complex.

Adding to the confusion, some of the tools that were developed to do automated analog design failed to recognize many of the variables that were important in making the design viable. One company burned huge amounts of venture capital with an outcome that allowed the automated design of op-amps. However, they were fixed in architecture, and the results were neither size or power optimized.

Not sure when computers are going to make this are obsolete, but its not on the horizon as of yet. The changing parameters associated with CMOS geometry changes has made the process even more difficult. Techniques to optimize become a moving target.

Title: Re: analog circuits synthesis tools
Post by carlgrace on Mar 4^th, 2011, 8:33am

loose-electron wrote on Jan 30^th, 2011, 5:46pm:

One company burned huge amounts of venture capital with an outcome that allowed the automated design of op-amps. However, they were fixed in architecture, and the results were neither size or power optimized.

Was this company named after a city in Spain?

Title: Re: analog circuits synthesis tools
Post by pirate on Dec 13^th, 2011, 5:55pm

barcelona design

Title: Re: analog circuits synthesis tools
Post by loose-electron on Dec 18^th, 2011, 5:18pm

in the last 20 years there have actual been a number of them who have tried and failed.

Never say never, but probably not in the next 10 years.