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Measurements >> Phase Noise and Jitter Measurements >> PLL input reference clock jitter spec
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Message started by lunren on Jan 26^th, 2011, 2:50pm

Title: PLL input reference clock jitter spec
Post by lunren on Jan 26^th, 2011, 2:50pm

Hi everyone,

I am now working on a PLL design. The customer said that I need give him a spec for the input reference clock jitter. The source of the input clock is not clear, maybe is from FPGA. If we assume it is FPGA, how can I get/derive a number for the input reference clock jitter? The spec of the PLL is:
Input clock: 20MHz
VCO gain: 2GHz/V
Output frequency: 400MHz
Loop bandwidth: 1MHz (starting point, should be within 500K to 2MHz).
Output cycle-2-cycle rms jitter: 2 degree

Any suggestion/comments on this are welcome.

Thanks

Title: Re: PLL input reference clock jitter spec
Post by rfidea on Jan 27^th, 2011, 1:31am

Since your PLL is multiplying the frequency of the reference with 400M/20M=20 the reference must be much better than 1/20 of the PLL spec, which is 2deg/20=0.1deg. That is within the bandwith of the PLL. At those frequencies the PLL is transparant for the the input jitter. Above the bandwith the PLL will attenuate the reference jitter.

So, the short answer is much better than 0.1deg

Title: Re: PLL input reference clock jitter spec
Post by lunren on Jan 28^th, 2011, 9:46am

rfidea wrote on Jan 27^th, 2011, 1:31am:

Since your PLL is multiplying the frequency of the reference with 400M/20M=20 the reference must be much better than 1/20 of the PLL spec, which is 2deg/20=0.1deg.

To me, it seems not correct. Assuming the PLL is ideal frequency multiplier, output_frequency=input_frequency*N. If we allow a 2 degree jitter on the output frequency, the input frequency jitter should also be 2 degree. Example is: output frequency period=10n±1n, then input frequency period should be: N*(10n±1n),
in terms of degree, it is the same.

Title: Re: PLL input reference clock jitter spec
Post by rfidea on Jan 28^th, 2011, 2:31pm

A noise free counter acting as a frequency divider will have the same timing-jitter at its output as at its input. The divider will "remove" all edges without the one that is switching the counter output. Since the output has a longer period time the jitter in degrees is smaller.

The frequency counter is placed in the feedback path of the PLL and will improve the jitter, in degrees, of the VCO at the phase detector input. Therefor the reference jitter must be much better than spec/N, in degrees.

Title: Re: PLL input reference clock jitter spec
Post by smlogan on Feb 8^th, 2011, 2:45pm

Hi Lunrun,

One procedure for determining the reference clock noise for a clock multiplier PLL is provided in the article at URL:

http://www.edn.com/article/457878-Specify_an_external_reference_clock_to_improve_SERDES_performance.php

This may be helpful to more rigorously determine the impact of the reference clock on the actual PLL output phase noise.

I hope this helps - at least I hope it helps your understanding.

Shawn