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Measurements >> Phase Noise and Jitter Measurements >> needs your comment: how to take power supply noise into account for PLL design
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Message started by lunren on Feb 8^th, 2011, 6:27pm

Title: needs your comment: how to take power supply noise into account for PLL design
Post by lunren on Feb 8^th, 2011, 6:27pm

Hi Everyone,

I am designing a PLL right now and facing a problem of how to deal with power supply ripple effect on PLL phase noise. I am trying to do in this way, but not sure if it make sense. Any comments/corrections/suggestions are welcome.

1) inject ripples of different frequency (one at a time) on power/sub for VCO test bench (frequency modulation) and do transient simulation
2) do FFT for the VCO output
3) based on FFT results, calculate phase noise @ offset frequency of injected ripple frequency
4) repeat the procedure for different ripple frequencies
5) in this way, I get the phase noise number at the output of VCO due to power supply ripple
6) I then use the closed loop transfer function (high pass) of VCO noise to calculate the phase noise contribution due to the power supply ripple at the output of PLL (treat the phase noise we got in step 5 the same way as VCO intrinsic noise, I think it is rational, since the power supply ripple and VCO intrinsic noise are totally uncorrelated)

I know people use PSS+PXF to test VCO's PSRR. But how to use this result to calculate its effect on PLL output (in closed loop fashion)?

Thanks,

Lunren

Title: Re: needs your comment: how to take power supply noise into account for PLL design
Post by lunren on Feb 9^th, 2011, 11:06pm

Well, it seems nobody is interested in this topic:).

After thinking for some time. I found the method has a problem. Now the new idea is:
1) model the power supply noise (as close as to the real power supply profile)
2) transient simulate the VCO block.
3) DFT the output waveform of VCO
4) calculate the phase noise from DFT results
5) use high pass transfer function of VCO noise and the phase noise results I get from step 4 to calculate power supply noise effect on the PLL's output phase noise.

The problem to me is how to calculate phase noise from DFT results?

Any suggestion/comments?

Thanks

Title: Re: needs your comment: how to take power supply noise into account for PLL design
Post by yxh12321 on Feb 18^th, 2011, 10:24pm

the same question

Title: Re: needs your comment: how to take power supply noise into account for PLL design
Post by sheldon on Feb 19^th, 2011, 6:47am

Greetings,

There are a couple of other options:
1) If the divide ratio is low enough you can use PSS/PXF to directly
calculate the power supply rejection.
2) You can use the Spectre RF noise aware PLL flow to accelerate
your transient simulations
a) When you generate the VCO model, include the power supply
effects in the model
b) You need to think about how to simulate the design, for
example, PFD, CP, and counters at transistor level with
the VCO and pre-scaler as behavioral

If you use the noise meter, you can directly access the impact
of the supply noise on the phase noise of the PLL using the
noise_meter.

Best Regards,

Sheldon