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Simulators >> Circuit Simulators >> Input referred offset of dynamic latch
https://designers-guide.org/forum/YaBB.pl?num=1298438962

Message started by Nandish Mehta on Feb 22^nd, 2011, 9:29pm

Title: Input referred offset of dynamic latch
Post by Nandish Mehta on Feb 22^nd, 2011, 9:29pm

Hello friends,

The latch that I have designed was proposed by Min et al in JSSC Dec 2003 for my application and is shown in the attached figure.

I am interested in simulating its worst case input referred offset under process variation, design corner and under 3-sigma mis-match.

Can any one please suggest me some method to estimate offset under above mentioned condition?

I will be very grateful to you for your inputs. I am very new to latch design and i am designing my first full chip.

Please kindly help.

Regards
Nandish

Title: Re: Input referred offset of dynamic latch
Post by ywguo on Feb 23^rd, 2011, 11:25pm

Hello,

Please have a look at http://www.designers-guide.org/Analysis/comparator.pdf.

A more simple way is explained below. This is proven to be effective if you have Cadence virtuoso, spectre simulator, and wavescan/VIVA.

make a slow ramp input for the comparator,
Run monte carlo simulation with mismatch only or process+mismatch.
then find the time when the comparator output toggles from 0 to 1, or 1 to 0, depending on the input signal increases or decreases.
Measure the input signal at that time.
At last the post-processing tool, like Wave Scan or Viva, will plot the histogram of the threshold voltage, with one sigma number. You can made a quick estimation of the max offset voltage with 6 sigma.

Best Regards,
Yawei

Title: Re: Input referred offset of dynamic latch
Post by Nandish Mehta on Feb 23^rd, 2011, 11:48pm

Hi Yawei,

Thank you so much !!! This is exactly what i was looking for. I read through the document you have posted. It is really awesome.

But I find your method more easier as I know how to do it.

Thanks a lot once again !!!

You really save lot of my design time....

Regards
Nandish