The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Other CAD Tools >> Physical Verification, Extraction and Analysis >> how to create xcell for calibre pex hierarchical extraction
https://designers-guide.org/forum/YaBB.pl?num=1300000927

Message started by lhlbluesky_lhl on Mar 12^th, 2011, 11:22pm

Title: how to create xcell for calibre pex hierarchical extraction
Post by lhlbluesky_lhl on Mar 12^th, 2011, 11:22pm

now, i want to extract the hierarchical pex netlist from layout using cadence calibre tool, but i don't know how to write the xcell list. can anyone help me for this? what is the format of xcell file? and how to create the xcell for hierarchical pex netlist extraction?

please help me, thanks.

Title: Re: how to create xcell for calibre pex hierarchical extraction
Post by ywguo on Jun 17^th, 2011, 6:52am

Hi,

Which CMOS process do you have? I recall that there is one xcell file in TSMC PDK. If you have TSMC PDK, you have a very good example.

Code:

cellL cellL
cellR cellR
cellM cellM

They are the cell names for layout in the left column, and the cell names for schematic in the right column.

I have a good tutorial for you, which I got a few years ago. But that is written in Chinese. Can you read Chinese?

Best Regards,
Yawei