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Other CAD Tools >> Physical Verification, Extraction and Analysis >> calibre parasitic extraction problem
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Message started by Tiger on Apr 10^th, 2011, 1:22am

Title: calibre parasitic extraction problem
Post by Tiger on Apr 10^th, 2011, 1:22am

hi, all.

I came across parasitci extraciton problems when using calibre, hope someone can help me:

The process i used provides deep nwell(DNW) for pusb isolation. So for some NFETs, I had S and B connected together to a different potential(net, suppose its name is Vx) from Gnd.

When run calibre c+cc parasitic extracion, i found the parasitic lumped capacitors of these NFETs, which are supposed to these isolated psub(net Vx), are to the whole pusb(net Gnd)~ Obviously, this is not correct.

So, how can i extract the parasitic capacitors correctly?

many thanks！

Tiger

Title: Re: calibre parasitic extraction problem
Post by boe on Apr 11^th, 2011, 10:26am

Tiger,

is your layout correct? I.e. does it have all guard rings etc. that your technology requires?
Did you test a single transistor?

B O E

Title: Re: calibre parasitic extraction problem
Post by Tiger on Apr 11^th, 2011, 8:00pm

Boe,

the layout is correct, and it is about different ground regions but the netlist is showing just one, which can be solved "Multiple Ground Regions" option.
And now, I've fixed my problem, which is just caused by the wrong "ground layer" name~