The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Other CAD Tools >> Physical Verification, Extraction and Analysis >> HELP TO SOLVE ERROR IN ABSTRACT EDITOR OF CADENCE
https://designers-guide.org/forum/YaBB.pl?num=1302763060

Message started by VINAY RAO on Apr 13^th, 2011, 11:37pm

Title: HELP TO SOLVE ERROR IN ABSTRACT EDITOR OF CADENCE
Post by VINAY RAO on Apr 13^th, 2011, 11:37pm

I tried out layout (for UMC180nm) in cadence but unable to solve some errors while generating LEF file. DRC,LVS, Parasitic extraction these are all passed. Even i am able to generate .gds file. Then i went for LEF from abstract but getting error which i attached to this topic.
I did layout for simple inverter then i am generating layout by using "Gen from Source" in layout XL.After everything (DRC,LVS,extraction, post layout simulation) been done, i selected abstract editor tool -> create abstract- finally it is generating error. I tried to solve by dumping technology file (technology.tf, by using TECHNOLOGY FILE MANAGER) into current working directory but by this also i got the same error. I am not understanding whether the problem is with the technology file which is given from foundry or some thing else. If any one could reply me it would be really helpful.

Title: Re: HELP TO SOLVE ERROR IN ABSTRACT EDITOR OF CADENCE
Post by ywguo on Jul 19^th, 2011, 11:43pm

Hi,

I come across the same problem when I generate LEF for a layout (SMIC 0.18um CMOS process).

I think this occurs because the technology file does not define routing layer and via. Have you worked out this issue? I am trying my best now.

Yawei