The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> Question about SJ https://designers-guide.org/forum/YaBB.pl?num=1306029049 Message started by newic on May 21st, 2011, 6:50pm

Title: Question about SJ Post by newic on May 21st, 2011, 6:50pm In pg7 Pattern Generator Model for Jitter-Tolerance Simulation discuss about SJ source. "When setting the parameters of the SJ component, care should be taken to avoid the sinusoidal jitter frequency to result from an integer or rational division of the clock frequency. Otherwise the sinusoidal jitter contribution may be insufficient covered by the simulation " What does it mean and the reason? Why dividing clk frequency by 2,3,4,5, 20, 50, 100 etc require long simulation to cover. The SJ frequency should be followed the jitter tolerance mask frequency right.

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