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https://designers-guide.org/forum/YaBB.pl General >> Tech Talk >> Universal Peripheral Bus Evolution https://designers-guide.org/forum/YaBB.pl?num=1307954078 Message started by sarangapani on Jun 13th, 2011, 1:34am |
Title: Universal Peripheral Bus Evolution Post by sarangapani on Jun 13th, 2011, 1:34am 1. Master 1. Read related Inputs 1. rd_clk 2. rd_addr_ready 3. rd_data_valid 4. rd_data 5. rd_response (Kinda rd_strobe) 2. Read related Outputs 1. rd_addr 2. rd_addr_valid 3. rd_transaction_id 3. Write related Inputs 1. wr_clk 2. wr_addr_ready 3. wr_data_ready 4. wr_response 4. Write related outputs 1. wr_addr 2. wr_data 3. wr_addr_valid 4. wr_data_valid 5. wr_strobe 6. wr_transaction_id Will all the above common port list will not be sufficient to have a Unified Peripheral Bus Protocol. I guess almost all existing bus protocols resembles the same port list kind. Then why cant be such Unified Peripheral Bus Protocol our Chip Industry follow, to avoid SOC hazzles. |
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