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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Extraction Problem in Cadence Assura
https://designers-guide.org/forum/YaBB.pl?num=1308746664

Message started by analog_design on Jun 22^nd, 2011, 5:44am

Title: Extraction Problem in Cadence Assura
Post by analog_design on Jun 22^nd, 2011, 5:44am

Hi,

When I do netlisting of av_extracted view of RC extracted layout. Aspect ratio of transistor is matching with schematic design. I mean, sizing of circuit (schematic) in netlist is not reflecting in extracted netlist. some time, if two device are in cascode position then, upper one's aspect ratio is reflected in lower one's size.

I do not where exactly going wrong? I believe it must be with model files. I am not sure about it.

Please, let me know your opinion and solution.

I would appreciate it.
Thank You,

Title: Re: Extraction Problem in Cadence Assura
Post by analog_design on Jun 22^nd, 2011, 5:45am

I am sorry (not matching with)